2009 |
30 | EE | Daniel Menard,
Emmanuel Casseau,
Shafqat Khan,
Olivier Sentieys,
Stéphane Chevobbe,
Stéphane Guyetant,
Raphaël David:
Reconfigurable Operator Based Multimedia Embedded Processor.
ARC 2009: 39-49 |
2008 |
29 | EE | Tuan-Duc Nguyen,
Olivier Berder,
Olivier Sentieys:
Impact of Transmission Synchronization Error and Cooperative Reception Techniques on the Performance of Cooperative MIMO Systems.
ICC 2008: 4601-4605 |
28 | EE | Antoine Courtay,
Johann Laurent,
Olivier Sentieys,
Nathalie Julien:
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses.
PATMOS 2008: 359-368 |
27 | EE | Julien Lallet,
Sébastien Pillement,
Olivier Sentieys:
Efficient dynamic reconfiguration for multi-context embedded FPGA.
SBCCI 2008: 210-215 |
26 | EE | Tuan-Duc Nguyen,
Olivier Berder,
Olivier Sentieys:
Efficient Space Time Combination Technique for Unsynchronized Cooperative Miso Transmission.
VTC Spring 2008: 629-633 |
25 | EE | Daniel Chillet,
Raphaël David,
E. Grâce,
Olivier Sentieys:
Structure mémoire reconfigurable. Vers une structure de stockage faible consommation.
Technique et Science Informatiques 27(1-2): 181-202 (2008) |
2007 |
24 | EE | Nicolas Hervé,
Daniel Menard,
Olivier Sentieys:
About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations.
ARC 2007: 191-200 |
23 | EE | Alexey Kupriyanov,
Frank Hannig,
Dmitrij Kissler,
Jürgen Teich,
Julien Lallet,
Olivier Sentieys,
Sébastien Pillement:
Modeling of Interconnection Networks in Massively Parallel Processor Architectures.
ARCS 2007: 268-282 |
22 | EE | Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures.
IJCNN 2007: 102-107 |
21 | EE | Tuan-Duc Nguyen,
Olivier Berder,
Olivier Sentieys:
Cooperative MIMO Schemes Optimal Selection for Wireless Sensor Networks.
VTC Spring 2007: 85-89 |
2006 |
20 | EE | Jean-Marc Philippe,
E. Kinvi-Boh,
Sébastien Pillement,
Olivier Sentieys:
An energy-efficient ternary interconnection link for asynchronous systems.
ISCAS 2006 |
19 | EE | R. Rocher,
Nicolas Hervé,
Daniel Menard,
Olivier Sentieys:
Fixed-point configurable hardware components for adaptive filters.
ISCAS 2006 |
18 | EE | Jean-Marc Philippe,
Sébastien Pillement,
Olivier Sentieys:
Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects.
ISQED 2006: 334-339 |
17 | | Stéphane Chevobbe,
Raphaël David,
Frédéric Blanc,
Thierry Collette,
Olivier Sentieys:
Control Unit for Parallel Embedded System.
ReCoSoC 2006: 168-176 |
2005 |
16 | EE | Jean-Marc Philippe,
Sébastien Pillement,
Olivier Sentieys:
A low-power and high-speed quaternary interconnection link using efficient converters.
ISCAS (5) 2005: 4689-4692 |
15 | | Frank Hannig,
Hritam Dutta,
Alexey Kupriyanov,
Jürgen Teich,
Rainer Schaffer,
Sebastian Siegel,
Renate Merker,
Ronan Keryell,
Bernard Pottier,
Daniel Chillet,
Daniel Menard,
Olivier Sentieys:
Co-Design of Massively Parallel Embedded Processor Architectures.
ReCoSoC 2005: 27-34 |
2004 |
14 | EE | Joel Cambonie,
Sylvain Guérin,
Ronan Keryell,
Loïc Lagadec,
Bernard Pottier,
Olivier Sentieys,
Bernt Weber,
Samar Yazdani:
Compiler and System Techniques for soc Distributed Reconfigurable Accelerators.
SAMOS 2004: 293-302 |
13 | EE | Daniel Menard,
Olivier Sentieys:
DSP Code Generation with Optimized Data Word-Length Selection.
SCOPES 2004: 214-228 |
2003 |
12 | EE | E. Kinvi-Boh,
M. Aline,
Olivier Sentieys,
Edgar "Dan" Olson:
MVL circuit design and characterization at the transistor level using SUS-LOC.
ISMVL 2003: 105-110 |
11 | EE | Daniel Menard,
Taofik Saïdi,
Daniel Chillet,
Olivier Sentieys:
Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe.
Technique et Science Informatiques 22(6): 783-803 (2003) |
2002 |
10 | EE | Daniel Menard,
Daniel Chillet,
François Charot,
Olivier Sentieys:
Automatic floating-point to fixed-point conversion for DSP code generation.
CASES 2002: 270-276 |
9 | EE | Daniel Menard,
Olivier Sentieys:
Automatic Evaluation of the Accuracy of Fixed-Point Algorithms.
DATE 2002: 529-537 |
8 | EE | Raphaël David,
Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
A Compilation Framework for a Dynamically Reconfigurable Architecture.
FPL 2002: 1058-1067 |
7 | EE | Raphaël David,
Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints.
IPDPS 2002 |
6 | EE | Sébastien Pillement,
Daniel Chillet,
Olivier Sentieys:
Behavioral IP Specification and Integration Framework for High-Level Design Reuse.
ISQED 2002: 388-393 |
2001 |
5 | | Raphaël David,
Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals.
VLSI-SOC 2001: 51-62 |
2000 |
4 | EE | Jean-Philippe Diguet,
Daniel Chillet,
Olivier Sentieys:
A Framework for High Level Estimations of Signal Processing VLSI Implementations.
VLSI Signal Processing 25(3): 261-284 (2000) |
1999 |
3 | EE | Daniel Chillet,
Olivier Sentieys,
Michel Corazza:
Memory Unit Design for Real Time DSP Applications.
Great Lakes Symposium on VLSI 1999: 260- |
2 | EE | J. O. Dedou,
Daniel Chillet,
Olivier Sentieys:
Behavioral synthesis of asynchronous systems: a methodology.
ISCAS (6) 1999: 370-373 |
1994 |
1 | EE | Michel Auguin,
Mohamed Belhadj,
Judith Benzakki,
C. Carrière,
Guy Durrieu,
Thierry Gautier,
Michel Israël,
Paul Le Guernic,
Michel Lemaître,
E. Martin,
P. Quinton,
Laurence Rideau,
François Rousseau,
Olivier Sentieys:
Towards a multi-formalism framework for architectural synthesis: the ASAR project.
CODES 1994: 25-32 |