| 2008 |
|---|
| 11 | EE | Siva Kumar Sastry Hari,
Vishnu Vardhan Reddy Konda,
V. Kamakoti,
Vivekananda M. Vedula,
K. S. Maneperambil:
Automatic Constraint Based Test Generation for Behavioral HDL Models.
IEEE Trans. VLSI Syst. 16(4): 408-421 (2008) |
| 2007 |
|---|
| 10 | EE | Sasidhar Sunkari,
Supratik Chakraborty,
Vivekananda M. Vedula,
Kailasnath Maneparambil:
A Scalable Symbolic Simulator for Verilog RTL.
MTV 2007: 51-59 |
| 9 | EE | K. Najeeb,
Karthik Gururaj,
V. Kamakoti,
Vivekananda M. Vedula:
Controllability-driven Power Virus Generation for Digital Circuits.
VLSI Design 2007: 407-412 |
| 8 | EE | K. Najeeb,
Vishnu Vardhan Reddy Konda,
Siva Kumar Sastry Hari,
V. Kamakoti,
Vivekananda M. Vedula:
Power Virus Generation Using Behavioral Models of Circuits.
VTS 2007: 35-42 |
| 2004 |
|---|
| 7 | EE | Vivekananda M. Vedula,
Whitney J. Townsend,
Jacob A. Abraham:
Program Slicing for ATPG-Based Property Checking.
VLSI Design 2004: 591-596 |
| 2003 |
|---|
| 6 | EE | Daniel G. Saab,
Jacob A. Abraham,
Vivekananda M. Vedula:
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines.
VLSI Design 2003: 243-248 |
| 5 | EE | Vivekananda M. Vedula,
Jacob A. Abraham,
Jayanta Bhadra,
Raghuram S. Tupuri:
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages.
J. Electronic Testing 19(2): 149-160 (2003) |
| 2002 |
|---|
| 4 | EE | Vivekananda M. Vedula,
Jacob A. Abraham:
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis.
DATE 2002: 730-735 |
| 3 | EE | Kamalnayan Jayaraman,
Vivekananda M. Vedula,
Jacob A. Abraham:
Native Mode Functional Self-Test Generation for Systems-on-Chip.
ISQED 2002: 280-285 |
| 2 | EE | Jacob A. Abraham,
Vivekananda M. Vedula,
Daniel G. Saab:
Verifying Properties Using Sequential ATPG.
ITC 2002: 194-202 |
| 1 | EE | Vivekananda M. Vedula,
Jacob A. Abraham,
Jayanta Bhadra:
Program Slicing for Hierarchical Test Generation.
VTS 2002: 237-246 |
