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Mukul R. Prasad

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2006
15EEIndradeep Ghosh, Mukul R. Prasad: A Technique for Estimating the Difficulty of a Formal Verification Problem. ISQED 2006: 63-70
2005
14EESubramanian K. Iyer, Jawahar Jain, Mukul R. Prasad, Debashis Sahoo, Thomas Sidle: Error Detection Using BMC in a Parallel Environment. CHARME 2005: 354-358
13EELiang Zhang, Mukul R. Prasad, Michael S. Hsiao: Interleaved Invariant Checking with Dynamic Abstraction. CHARME 2005: 81-96
12EELiang Zhang, Mukul R. Prasad, Michael S. Hsiao, Thomas Sidle: Dynamic abstraction using SAT-based BMC. DAC 2005: 754-757
11EEMukul R. Prasad, Armin Biere, Aarti Gupta: A survey of recent advances in SAT-based formal verification. STTT 7(2): 156-173 (2005)
2004
10EELiang Zhang, Mukul R. Prasad, Michael S. Hsiao: Incremental deductive & inductive reasoning for SAT-based bounded model checking. ICCAD 2004: 502-509
9EEMukul R. Prasad, Michael S. Hsiao, Jawahar Jain: Can SAT be used to Improve Sequential ATPG Methods? VLSI Design 2004: 585-
8EEIndradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita: High Level Design Validation: Current Practices and Future Directions. VLSI Design 2004: 9-11
2003
7EEKelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain: Solving the latch mapping problem in an industrial setting. DAC 2003: 442-447
2002
6EEEvguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton: Using Problem Symmetry in Search Based Satisfiability Algorithms. DATE 2002: 134-141
5 Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain: Improving Sequential ATPG Using SAT Methods. IWLS 2002: 79-84
2001
4EEEvguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton: Using SAT for combinational equivalence checking. DATE 2001: 114-121
3EEMukul R. Prasad, Philip Chong, Kurt Keutzer: Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits? J. Electronic Testing 17(6): 509-527 (2001)
1999
2EEMukul R. Prasad, Philip Chong, Kurt Keutzer: Why is ATPG Easy? DAC 1999: 22-28
1996
1EEC. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora: Estimation of Power from Module-level Netlists. VLSI Design 1996: 324-325

Coauthor Index

1Armin Biere [11]
2Robert K. Brayton [4] [6]
3Philip Chong [2] [3]
4Masahiro Fujita [8]
5Indradeep Ghosh [8] [15]
6Eugene Goldberg (Evguenii I. Goldberg) [4] [6]
7Aarti Gupta [11]
8Lavmeet S. Hora [1]
9Michael S. Hsiao [5] [9] [10] [12] [13]
10Subramanian K. Iyer [14]
11Jawahar Jain [5] [7] [9] [14]
12Kurt Keutzer [2] [3]
13Rajarshi Mukherjee [7] [8]
14Kelvin Ng [7]
15C. P. Ravikumar [1]
16Debashis Sahoo [14]
17Thomas Sidle [12] [14]
18Liang Zhang [10] [12] [13]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)