2006 |
15 | EE | Indradeep Ghosh,
Mukul R. Prasad:
A Technique for Estimating the Difficulty of a Formal Verification Problem.
ISQED 2006: 63-70 |
2005 |
14 | EE | Subramanian K. Iyer,
Jawahar Jain,
Mukul R. Prasad,
Debashis Sahoo,
Thomas Sidle:
Error Detection Using BMC in a Parallel Environment.
CHARME 2005: 354-358 |
13 | EE | Liang Zhang,
Mukul R. Prasad,
Michael S. Hsiao:
Interleaved Invariant Checking with Dynamic Abstraction.
CHARME 2005: 81-96 |
12 | EE | Liang Zhang,
Mukul R. Prasad,
Michael S. Hsiao,
Thomas Sidle:
Dynamic abstraction using SAT-based BMC.
DAC 2005: 754-757 |
11 | EE | Mukul R. Prasad,
Armin Biere,
Aarti Gupta:
A survey of recent advances in SAT-based formal verification.
STTT 7(2): 156-173 (2005) |
2004 |
10 | EE | Liang Zhang,
Mukul R. Prasad,
Michael S. Hsiao:
Incremental deductive & inductive reasoning for SAT-based bounded model checking.
ICCAD 2004: 502-509 |
9 | EE | Mukul R. Prasad,
Michael S. Hsiao,
Jawahar Jain:
Can SAT be used to Improve Sequential ATPG Methods?
VLSI Design 2004: 585- |
8 | EE | Indradeep Ghosh,
Rajarshi Mukherjee,
Mukul R. Prasad,
Masahiro Fujita:
High Level Design Validation: Current Practices and Future Directions.
VLSI Design 2004: 9-11 |
2003 |
7 | EE | Kelvin Ng,
Mukul R. Prasad,
Rajarshi Mukherjee,
Jawahar Jain:
Solving the latch mapping problem in an industrial setting.
DAC 2003: 442-447 |
2002 |
6 | EE | Evguenii I. Goldberg,
Mukul R. Prasad,
Robert K. Brayton:
Using Problem Symmetry in Search Based Satisfiability Algorithms.
DATE 2002: 134-141 |
5 | | Mukul R. Prasad,
Michael S. Hsiao,
Jawahar Jain:
Improving Sequential ATPG Using SAT Methods.
IWLS 2002: 79-84 |
2001 |
4 | EE | Evguenii I. Goldberg,
Mukul R. Prasad,
Robert K. Brayton:
Using SAT for combinational equivalence checking.
DATE 2001: 114-121 |
3 | EE | Mukul R. Prasad,
Philip Chong,
Kurt Keutzer:
Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits?
J. Electronic Testing 17(6): 509-527 (2001) |
1999 |
2 | EE | Mukul R. Prasad,
Philip Chong,
Kurt Keutzer:
Why is ATPG Easy?
DAC 1999: 22-28 |
1996 |
1 | EE | C. P. Ravikumar,
Mukul R. Prasad,
Lavmeet S. Hora:
Estimation of Power from Module-level Netlists.
VLSI Design 1996: 324-325 |