2008 | ||
---|---|---|
32 | EE | Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Koji Inoue: Improved Policies for Drowsy Caches in Embedded Processors. DELTA 2008: 362-367 |
31 | EE | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii: CHStone: A benchmark program suite for practical C-based high-level synthesis. ISCAS 2008: 1192-1195 |
30 | EE | Shan Ding, Hiroyuki Tomiyama, Hiroaki Takada: An Effective GA-Based Scheduling Algorithm for FlexRay Systems. IEICE Transactions 91-D(8): 2115-2123 (2008) |
2007 | ||
29 | EE | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii: Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis. ACM Great Lakes Symposium on VLSI 2007: 365-370 |
28 | EE | Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada: RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip. ASP-DAC 2007: 336-341 |
27 | EE | Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada: A Software Framework for Energy and Performance Tradeoff in Fixed-Priority Hard Real-Time Embedded Systems. EUC 2007: 13-24 |
26 | EE | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii: Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study. ICESS 2007: 261-270 |
25 | EE | Takashi Furukawa, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada: A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems. ICESS 2007: 283-294 |
24 | EE | Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada: Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt Services. IESS 2007: 241-254 |
23 | EE | Shan Ding, Hiroyuki Tomiyama, Hiroaki Takada: Scheduling Algorithms for I/O Blockings with a Multi-frame Task Model. RTCSA 2007: 386-393 |
22 | EE | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii: Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis. IEICE Transactions 90-A(12): 2853-2862 (2007) |
21 | EE | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada: Function Call Optimization for Efficient Behavioral Synthesis. IEICE Transactions 90-A(9): 2032-2036 (2007) |
2006 | ||
20 | EE | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada: Function Call Optimization in Behavioral Synthesis. DSD 2006: 522-529 |
2005 | ||
19 | EE | Shan Ding, Naohiko Murakami, Hiroyuki Tomiyama, Hiroaki Takada: A GA-based scheduling method for FlexRay systems. EMSOFT 2005: 110-113 |
18 | EE | Hiroshi Miyamoto, Shinichi Iiyama, Hiroyuki Tomiyama, Hiroaki Takada, Hiroshi Nakashima: An Efficient Search Algorithm of Worst-Case Cache Flush Timings. RTCSA 2005: 45-52 |
17 | EE | Hiroyuki Tomiyama, Shin-ichiro Chikada, Shinya Honda, Hiroaki Takada: An RTOS-Based Design and Validation Methodology for Embedded Systems. IEICE Transactions 88-D(9): 2205-2208 (2005) |
2004 | ||
16 | EE | Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiyama, Hiroaki Takada: RTOS-centric hardware/software cosimulator for embedded system design. CODES+ISSS 2004: 158-163 |
2003 | ||
15 | Hiroyuki Tomiyama, Hiroaki Takada, Nikil D. Dutt: Data Organization Exploration for Low-Energy Address Buses. ESTImedia 2003: 128-133 | |
2002 | ||
14 | EE | Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama: Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. DATE 2002: 36-43 |
13 | EE | Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao: Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems. ISSS 2002: 201-206 |
12 | EE | Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. VLSI Design 2002: 458- |
2001 | ||
11 | EE | Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama, Ashok Halambi: New directions in compiler technology for embedded systems (embedded tutorial). ASP-DAC 2001: 409-414 |
10 | EE | Anupam Datta, Sidharth Choudhury, Anupam Basu, Hiroyuki Tomiyama, Nikil Dutt: Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique. VLSI Design 2001: 97-102 |
2000 | ||
9 | EE | Hiroyuki Tomiyama, Nikil D. Dutt: Program path analysis to bound cache-related preemption delay in preemptive real-time systems. CODES 2000: 67-71 |
1998 | ||
8 | Hiroyuki Tomiyama, Hiroto Yasuura: Module Selection Using Manufacturing Information. ASP-DAC 1998: 275-281 | |
7 | EE | Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura: Instruction Scheduling for Power Reduction in Processor-Based System Design. DATE 1998: 855-860 |
6 | EE | Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura: Instruction Encoding Techniques for Area Minimization of Instruction ROM. ISSS 1998: 125-130 |
5 | EE | Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura: Statistical Performance-Driven Module Binding in High-Level Synthesis. ISSS 1998: 66-71 |
4 | EE | Hiroto Yasuura, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar: Embedded System Design Using Soft-Core Processor and Valen-C. J. Inf. Sci. Eng. 14(3): 587-603 (1998) |
1997 | ||
3 | EE | Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura: Memory-CPU Size Optimization for Embedded System Designs. DAC 1997: 246-251 |
2 | EE | Hiroyuki Tomiyama, Hiroto Yasuura: Code placement techniques for cache miss rate reduction. ACM Trans. Design Autom. Electr. Syst. 2(4): 410-429 (1997) |
1996 | ||
1 | EE | Hiroyuki Tomiyama, Hiroto Yasuura: Size-Constrained Code Placement for Cache Miss Rate Reduction. ISSS 1996: 96-104 |