2007 |
10 | EE | Paul Wielage,
Erik Jan Marinissen,
Michel Altheimer,
Clemens Wouters:
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO.
DATE 2007: 853-858 |
9 | EE | Tobias Dubois,
Erik Jan Marinissen,
Mohamed Azimane,
Paul Wielage,
Erik Larsson,
Clemens Wouters:
Test quality analysis and improvement for an embedded asynchronous FIFO.
DATE 2007: 859-864 |
2005 |
8 | EE | Andrei Radulescu,
John Dielissen,
Santiago González Pestana,
Om Prakash Gangwal,
Edwin Rijpkema,
Paul Wielage,
Kees G. W. Goossens:
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 4-17 (2005) |
2004 |
7 | EE | Andrei Radulescu,
John Dielissen,
Kees G. W. Goossens,
Edwin Rijpkema,
Paul Wielage:
An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration.
DATE 2004: 878-883 |
2003 |
6 | EE | Edwin Rijpkema,
Kees G. W. Goossens,
Andrei Radulescu,
John Dielissen,
Jef L. van Meerbergen,
Paul Wielage,
E. Waterlander:
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip.
DATE 2003: 10350-10355 |
5 | EE | Joep L. W. Kessels,
Ad M. G. Peeters,
Paul Wielage,
Suk-Jin Kim:
Clock synchronization through handshake signalling.
Microprocessors and Microsystems 27(9): 447-460 (2003) |
2002 |
4 | EE | Joep L. W. Kessels,
Suk-Jin Kim,
Ad M. G. Peeters,
Paul Wielage:
Clock Synchronization through Handshake Signalling.
ASYNC 2002: 59-68 |
3 | EE | Kees G. W. Goossens,
Paul Wielage,
Ad M. G. Peeters,
Jef L. van Meerbergen:
Networks on Silicon: Combining Best-Effort and Guaranteed Services.
DATE 2002: 423-427 |
2 | EE | Paul Wielage,
Kees G. W. Goossens:
Networks on Silicon: Blessing or Nightmare?
DSD 2002: 196-200 |
2001 |
1 | EE | Richard P. Kleihorst,
Anteneh A. Abbo,
André van der Avoird,
M. Op de Beeck,
Leo Sevat,
Paul Wielage,
R. van Veen,
H. van Herten:
Xetal: a low-power high-performance smart camera processor.
ISCAS (5) 2001: 215-218 |