| 2007 |
|---|
| 10 | EE | Jacques Benkoski,
Michelle Clancy,
Shankar Krishnamoorthy,
David Holt,
Ravi Subramanian,
Clive Bittlestone,
Tsuyoshi Yamamoto,
Andrew Kanhg:
Do Digital Design and Variability Mix like Oil and Water?
ISQED 2007: 672-676 |
| 2002 |
|---|
| 9 | EE | K. Brock,
C. Edwards,
R. Lannoo,
Ulf Schlichtmann,
Antun Domic,
Jacques Benkoski,
David Overhauser,
M. Kliment:
Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs.
DATE 2002: 538-539 |
| 2001 |
|---|
| 8 | EE | Bill Alexander,
Jacques Benkoski:
0.13 micron: Will the Speed Bumps Slow the Race to Market?
ISQED 2001: 229- |
| 2000 |
|---|
| 7 | EE | Robert N. Blair,
Jacques Benkoski:
How Do You Select A High Quality EDA Tool Flow?.
ISQED 2000: 17- |
| 1991 |
|---|
| 6 | EE | Jacques Benkoski,
Andrzej J. Strojwas:
The Role of Timing Verification in Layout Synthesis.
DAC 1991: 612-619 |
| 5 | | Ronald Stewart,
Jacques Benkoski:
Static Timing Analysis Using Interval Constraints.
ICCAD 1991: 308-311 |
| 1990 |
|---|
| 4 | EE | Jacques Benkoski,
E. Vanden Meersch,
Luc J. M. Claesen,
Hugo De Man:
Timing verification using statically sensitizable paths.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(10): 10723-10784 (1990) |
| 1989 |
|---|
| 3 | EE | Jacques Benkoski,
Andrzej J. Strojwas:
Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator.
DAC 1989: 668-673 |
| 2 | | Jacques Benkoski,
Andrzej J. Strojwas:
Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator.
ITC 1989: 153-160 |
| 1987 |
|---|
| 1 | EE | Jacques Benkoski,
Andrzej J. Strojwas:
A New Approach to Hierarchical and Statistical Timing Simulations.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(6): 1039-1052 (1987) |
