Maciej J. Ciesielski

2008
42	EE	Kyuho Shim, Youngrae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang: A fast two-pass HDL simulation with on-demand dump. ASP-DAC 2008: 422-427
41	EE	Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang: Simulation Acceleration with HW Re-Compilation Avoidance. VLSI Design 2008: 487-491
2007
40	EE	Maciej J. Ciesielski, Serkan Askar, D. Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon: Data-flow transformations using Taylor expansion diagrams. DATE 2007: 455-460
2006
39	EE	Jérémie Guillot, Emmanuel Boutillon, Q. Ren, Maciej J. Ciesielski, D. Gomez-Prado, Serkan Askar: Efficient factorization of DSP transforms using taylor expansion diagrams. DATE 2006: 754-755
38	EE	Maciej J. Ciesielski, Priyank Kalla, Serkan Askar: Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. IEEE Trans. Computers 55(9): 1188-1201 (2006)
2005
37	EE	Zhaojun Wo, Israel Koren, Maciej J. Ciesielski: An ILP Formulation for Yield-driven Architectural Synthesis. DFT 2005: 12-20
36	EE	Zhaojun Wo, Israel Koren, Maciej J. Ciesielski: Yield-aware Floorplanning. DSD 2005: 247-253
35	EE	Zhihong Zeng, Kesava R. Talupuru, Maciej J. Ciesielski: Functional test generation based on word-level SAT. Journal of Systems Architecture 51(8): 488-511 (2005)
2004
34	EE	Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski: A new state assignment technique for testing and low power. DAC 2004: 510-513
33	EE	Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski: Algorithms for Taylor Expansion Diagrams. ISMVL 2004: 235-240
2003
32	EE	Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski: Fast Computation of Data Correlation Using BDDs. DATE 2003: 10122-10129
2002
31	EE	Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre: Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. DATE 2002: 285-291
30	EE	Maciej J. Ciesielski, Serkan Askar, Samuel Levitin: Analytical approach to layout generation of datapath cells. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1480-1488 (2002)
29	EE	Priyank Kalla, Maciej J. Ciesielski: A comprehensive approach to the partial scan problem using implicitstate enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 810-826 (2002)
28	EE	Congguang Yang, Maciej J. Ciesielski: BDS: a BDD-based logic optimization system. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 866-876 (2002)
2001
27	EE	Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski: LPSAT: a unified approach to RTL satisfiability. DATE 2001: 398-402
26		Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre: Functional Test Generation using Constraint Logic Programming. VLSI-SOC 2001: 375-387
2000
25	EE	Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal: BDS: a BDD-based logic optimization system. DAC 2000: 92-97
24	EE	Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang: A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm. DATE 2000: 232-236
23	EE	Congguang Yang, Maciej J. Ciesielski: Synthesis for Mixed CMOS/PTl Logic. DATE 2000: 750
22	EE	Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski: Retiming-based factorization for sequential logic optimization. ACM Trans. Design Autom. Electr. Syst. 5(3): 373-398 (2000)
1999
21	EE	Priyank Kalla, Maciej J. Ciesielski: Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. DATE 1999: 638-642
20	EE	Serkan Askar, Maciej J. Ciesielski: Analytical approach to custom datapath design. ICCAD 1999: 98-101
19	EE	Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal: BDD Decomposition for Efficient Logic Synthesis. ICCD 1999: 626-
18	EE	Durgam Vahia, Maciej J. Ciesielski: Transistor level placement for full custom datapath cell design. ISPD 1999: 158-163
1998
17	EE	Balakrishnan Iyer, Maciej J. Ciesielski: Reencoding for cycle-time minimization under fixed encoding length. ICCAD 1998: 312-315
16	EE	Priyank Kalla, Maciej J. Ciesielski: A comprehensive approach to the partial scan problem using implicit state enumeration. ITC 1998: 651-657
15	EE	Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu: Wave-pipelining: a tutorial and research survey. IEEE Trans. VLSI Syst. 6(3): 464-474 (1998)
1997
14		Imrich Chlamtac, Maciej J. Ciesielski, Andrea Fumagalli, Chester A. Ruszczyk, Gosse Wedzinga: Intelligent Simulation for Computer Aided Design of Optical Networks. ONDM 1997: 73-86
13	EE	Priyank Kalla, Maciej J. Ciesielski: Testability of Sequential Circuits with Multi-Cycle False Path. VTS 1997: 322-328
1996
12	EE	Balakrishnan Iyer, Maciej J. Ciesielski: Metamorphosis: state assignment by retiming and re-encoding. ICCAD 1996: 614-617
1994
11		Wayne Burleson, L. W. Cotten, Fabian Klass, Maciej J. Ciesielski: Forum: Wave-pipelining: Is it Practical? ISCAS 1994: 163-166
1993
10	EE	Donald A. Joy, Maciej J. Ciesielski: Clock period minimization with wave pipelining. IEEE Trans. on CAD of Integrated Circuits and Systems 12(4): 461-472 (1993)
1992
9		Maya K. Yajnik, Maciej J. Ciesielski: Finite State Machine Decomposition Using Multiway Partitioning. ICCD 1992: 320-323
8	EE	Zafar Hasan, David Harrison, Maciej J. Ciesielski: A Fast Partitioning Method for PLA-Based FPGAs. IEEE Design & Test of Computers 9(4): 34-39 (1992)
7	EE	Maciej J. Ciesielski, Seiyang Yang: PLADE: a two-stage PLA decomposition. IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 943-954 (1992)
1991
6	EE	Maciej J. Ciesielski, Jia-Jye Shen, Marc Davio: A Unified Approach to Input-Output Encoding for FSM State Assignment. DAC 1991: 176-181
5	EE	Donald A. Joy, Maciej J. Ciesielski: Placement for Clock Period Minimization With Multiple Wave Propagation. DAC 1991: 640-643
4	EE	Seiyang Yang, Maciej J. Ciesielski: Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 4-12 (1991)
1989
3	EE	Maciej J. Ciesielski: Layer assignment for VLSI interconnect delay minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 8(6): 702-707 (1989)
1987
2	EE	Maciej J. Ciesielski, E. Kinnen: Digraph Relaxation for 2-Dimensional Placement of IC Blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 6(1): 55-66 (1987)
1985
1	EE	Maciej J. Ciesielski: Two-Dimensional Routing for the Silc Silicon Compiler. IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 198-203 (1985)

Coauthor Index

1	Serkan Askar	[20] [30] [38] [39] [40]
2	Hyuncheol Baik	[42]
3	Surendra Bommu	[22]
4	Emmanuel Boutillon	[39] [40]
5	Wayne P. Burleson (Wayne Burleson)	[11] [15]
6	Imrich Chlamtac	[14]
7	Sangwook Cho	[34]
8	Youngrae Cho	[42]
9	Kyumyung Choi	[42]
10	L. W. Cotten	[11]
11	Marc Davio	[6]
12	Rolf Drechsler	[33]
13	Görschwin Fey	[33]
14	Andrea Fumagalli	[14]
15	D. Gomez-Prado	[39] [40]
16	Jérémie Guillot	[39] [40]
17	Ian G. Harris	[32]
18	David Harrison	[8]
19	Zafar Hasan	[8]
20	ChiLai Huang	[24]
21	Balakrishnan Iyer	[12] [17]
22	Donald A. Joy	[5] [10]
23	Priyank Kalla	[13] [16] [21] [24] [27] [29] [31] [38]
24	Dusung Kim	[42]
25	Jaebum Kim	[42]
26	Kyungkuk Kim	[42]
27	Namdo Kim	[42]
28	E. Kinnen	[2]
29	Fabian Klass	[11] [15]
30	Israel Koren	[36] [37]
31	Samuel Levitin	[30]
32	W. Liu	[15]
33	Byeongun Min	[42]
34	Niall O'Neill	[22]
35	Sungju Park	[34]
36	Q. Ren	[39]
37	Bruno Rouzeyre	[26] [31]
38	Chester A. Ruszczyk	[14]
39	Jia-Jye Shen	[6]
40	Kyuho Shim	[41] [42]
41	Vigyan Singhal	[19] [25]
42	Kesava R. Talupuru	[35] [41]
43	Durgam Vahia	[18]
44	Gosse Wedzinga	[14]
45	Zhaojun Wo	[36] [37]
46	Maya K. Yajnik	[9]
47	Congguang Yang	[19] [23] [25] [28]
48	Seiyang Yang	[4] [7] [34] [41] [42]
49	Zhihong Zeng	[24] [26] [27] [31] [32] [35]
50	Qiushuang Zhang	[32]

Colors in the list of coauthors