Erik Jan Marinissen

2009
49	EE	Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty: Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. IEEE Trans. Computers 58(3): 409-423 (2009)
2008
48	EE	Ozgur Sinanoglu, Erik Jan Marinissen: Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing. DATE 2008: 182-187
2007
47	EE	Paul Wielage, Erik Jan Marinissen, Michel Altheimer, Clemens Wouters: Design and DfT of a high-speed area-efficient embedded asynchronous FIFO. DATE 2007: 853-858
46	EE	Tobias Dubois, Erik Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson, Clemens Wouters: Test quality analysis and improvement for an embedded asynchronous FIFO. DATE 2007: 859-864
45	EE	Sandeep Kumar Goel, Erik Jan Marinissen: On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips CoRR abs/0710.4687: (2007)
44	EE	Erik Jan Marinissen, Axel Jantsch, Nicola Nicolici: DATE 07 workshop on diagnostic services in NoCs. IEEE Design & Test of Computers 24(5): 510 (2007)
2006
43	EE	Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty: Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. DATE 2006: 285-290
42	EE	Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes: Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism. European Test Symposium 2006: 213-218
41	EE	Mitra Subhasish, Ondrej Novák, Hana Kubatova, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar: Conference Reports. IEEE Design & Test of Computers 23(4): 262-265 (2006)
2005
40	EE	Tom Waayers, Erik Jan Marinissen, Maurice Lousberg: IEEE Std 1500 Compliant Infrastructure forModular SOC Testing. Asian Test Symposium 2005: 450
39	EE	Sandeep Kumar Goel, Erik Jan Marinissen: On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. DATE 2005: 44-49
38	EE	Erik Jan Marinissen, Betty Prince, Doris Keitel-Schulz, Yervant Zorian: Challenges in Embedded Memory Design and Test. DATE 2005: 722-727
37	EE	Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen: Optimal Interconnect ATPG Under a Ground-Bounce Constraint. J. Electronic Testing 21(1): 17-31 (2005)
2004
36	EE	Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk: Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. DATE 2004: 108-113
35	EE	Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty: IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. ITC 2004: 1203-1212
34	EE	Erik Jan Marinissen: Security vs. Test Quality: Can We Really Only Have One at a Time? ITC 2004: 1411
33	EE	Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge: Trends in Testing Integrated Circuits. ITC 2004: 688-697
2003
32	EE	Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Müller: Creating Value Through Test. DATE 2003: 10402-10409
31	EE	Sandeep Kumar Goel, Erik Jan Marinissen: Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. DATE 2003: 10738-10741
30	EE	Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen: Optimal Interconnect ATPG Under a Ground-Bounce Constraint. ITC 2003: 369-378
29	EE	Sandeep Kumar Goel, Erik Jan Marinissen: SOC test architecture design for efficient utilization of test bandwidth. ACM Trans. Design Autom. Electr. Syst. 8(4): 399-429 (2003)
28	EE	Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts: Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. IEEE Design & Test of Computers 20(2): 8-18 (2003)
27	EE	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip. IEEE Trans. Computers 52(12): 1619-1632 (2003)
26	EE	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Efficient test access mechanism optimization for system-on-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 635-643 (2003)
25	EE	Sandeep Kumar Goel, Erik Jan Marinissen: A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. J. Electronic Testing 19(4): 425-435 (2003)
2002
24	EE	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. Asian Test Symposium 2002: 320-
23	EE	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. DAC 2002: 685-690
22	EE	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Efficient Wrapper/TAM Co-Optimization for Large SOCs. DATE 2002: 491-498
21	EE	Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty: Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. ITC 2002: 1159-1168
20	EE	Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty: A Set of Benchmarks fo Modular Testing of SOCs. ITC 2002: 519-528
19	EE	Sandeep Kumar Goel, Erik Jan Marinissen: Effective and Efficient Test Architecture Design for SOCs. ITC 2002: 529-538
18	EE	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. VTS 2002: 253-258
17	EE	Sandeep Kumar Goel, Erik Jan Marinissen: Cluster-Based Test Architecture Design for System-on-Chip. VTS 2002: 259-264
16		Krishnendu Chakrabarty, Erik Jan Marinissen: How Useful are the ITC 02 SoC Test Benchmarks? IEEE Design & Test of Computers 19(5): 120, 119 (2002)
15	EE	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. J. Electronic Testing 18(2): 213-230 (2002)
14	EE	Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian: On IEEE P1500's Standard for Embedded Core Test. J. Electronic Testing 18(4-5): 365-383 (2002)
13	EE	Erik Jan Marinissen: The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs. J. Electronic Testing 18(4-5): 435-454 (2002)
2001
12		Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Test wrapper and test access mechanism co-optimization for system-on-chip. ITC 2001: 1023-1032
11		Erik Jan Marinissen: An Industrial Approach to Core-Based System Chip Testing. VLSI-SOC 2001: 389-400
10	EE	Gundolf Kiefer, Harald P. E. Vranken, Erik Jan Marinissen, Hans-Joachim Wunderlich: Application of Deterministic Logic BIST on Industrial Circuits. J. Electronic Testing 17(3-4): 351-362 (2001)
2000
9	EE	Yervant Zorian, Erik Jan Marinissen: System chip test: how will it impact your design? DAC 2000: 136-141
8		Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen: Application of deterministic logic BIST on industrial circuits. ITC 2000: 105-114
7		Yervant Zorian, Erik Jan Marinissen, Rohit Kapur: On using IEEE P1500 SECT for test plug-n-play. ITC 2000: 770-777
6		Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel: Wrapper design for embedded core test. ITC 2000: 911-920
1999
5		Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel: Towards a standard for embedded core test: an example. ITC 1999: 616-627
4		Yervant Zorian, Erik Jan Marinissen, Sujit Dey: Testing Embedded-Core-Based System Chips. IEEE Computer 32(6): 52-60 (1999)
1998
3	EE	Yervant Zorian, Erik Jan Marinissen, Sujit Dey: Testing embedded-core based system chips. ITC 1998: 130-
2	EE	Erik Jan Marinissen, Robert G. J. Arendsen, Gerard Bos, Hans Dingemanse, Maurice Lousberg, Clemens Wouters: A structured and scalable mechanism for test access to embedded reusable cores. ITC 1998: 284-293
1	EE	Joep Aerts, Erik Jan Marinissen: Scan chain design for test time reduction in core-based ICs. ITC 1998: 448-457

Coauthor Index

1	Joep Aerts	[1]
2	Bashir M. Al-Hashimi	[41]
3	Michel Altheimer	[47]
4	Alexandre M. Amory	[42]
5	Robert G. J. Arendsen	[2]
6	Mohamed Azimane	[46]
7	Ben Bennetts (R. G. Bennetts)	[28]
8	Gerard Bos	[2]
9	Krishnendu Chakrabarty	[12] [15] [16] [18] [20] [21] [22] [23] [24] [26] [27] [35] [43] [49]
10	Kuoshu Chiu	[36]
11	Sujit Dey	[3] [4]
12	Hans Dingemanse	[2]
13	Tobias Dubois	[46]
14	Sandeep Kumar Goel	[6] [17] [19] [21] [25] [29] [31] [35] [36] [39] [43] [45] [49]
15	Kees G. W. Goossens (Kees Goossens)	[42]
16	Henk D. L. Hollmann	[28] [30] [37]
17	Camelia Hora	[33]
18	Vikram Iyengar	[12] [15] [18] [20] [21] [22] [23] [24] [26] [27]
19	Axel Jantsch	[44]
20	Rohit Kapur	[5] [7] [14]
21	Doris Keitel-Schulz	[38]
22	Michael Kessler	[32]
23	Gundolf Kiefer	[8] [10]
24	Bram Kruseman	[33]
25	Hana Kubatova	[41]
26	Erik Larsson	[46]
27	Maurice Lousberg	[2] [6] [14] [40]
28	Marcelo Lubaszewski	[42]
29	Robert Madge	[32]
30	Teresa L. McLaurin	[14]
31	Fernando Gehm Moraes (Fernando Moraes)	[42]
32	Michael Müller	[32]
33	Toan Nguyen	[36]
34	Nicola Nicolici	[44]
35	Ondrej Novák	[41]
36	Steven Oostdijk	[36]
37	Betty Prince	[38]
38	C. P. Ravikumar	[41]
39	Mike Ricchetti	[14]
40	Robert Van Rijsinge	[33]
41	Anuja Sehgal	[35] [43] [49]
42	Ozgur Sinanoglu	[48]
43	Mitra Subhasish	[41]
44	Tony Taylor	[5]
45	Bart Vermeulen	[28] [30] [32] [33] [37]
46	Harald P. E. Vranken	[8] [10]
47	Tom Waayers	[40]
48	Lee Whetsel	[5]
49	Paul Wielage	[46] [47]
50	Clemens Wouters	[2] [46] [47]
51	Hans-Joachim Wunderlich	[8] [10]
52	Yervant Zorian	[3] [4] [5] [6] [7] [9] [14] [38]

Colors in the list of coauthors