Michel R. C. M. Berkelaar

2004
12	EE	Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz: Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. ICCD 2004: 350-353
2002
11	EE	Michel R. C. M. Berkelaar, Koen van Eijk: Efficient and Effective Redundancy Removal for Million-Gate Circuits. DATE 2002: 1088
2000
10	EE	E. T. A. F. Jacobs, Michel R. C. M. Berkelaar: Gate Sizing Using a Statistical Delay Model. DATE 2000: 283-
1998
9	EE	J. W. J. M. Rutten, Michel R. C. M. Berkelaar, C. A. J. van Eijk, M. A. J. Kolsteren: An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization. DATE 1998: 749-754
8	EE	Harm Arts, Michel R. C. M. Berkelaar, Koen van Eijk: Computing observability don't cares efficiently through polarization. IEEE Trans. on CAD of Integrated Circuits and Systems 17(7): 573-581 (1998)
1997
7	EE	J. W. J. M. Rutten, Michel R. C. M. Berkelaar: Improved State Assignment for Burst Mode Finite State Machines. ASYNC 1997: 228-239
1996
6	EE	Harm Arts, Michel R. C. M. Berkelaar, C. A. J. van Eijk: Polarized observability don't cares. ICCAD 1996: 626-631
5	EE	Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess: Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 15(11): 1424-1434 (1996)
1995
4	EE	Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken: Efficient orthonormality testing for synthesis with pass-transistor selectors. ICCAD 1995: 256-263
3	EE	Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, S. Prakash: Efficient use of large don't cares in high-level and logic synthesis. ICCAD 1995: 272-278
1994
2	EE	Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess: Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. ICCAD 1994: 474-480
1990
1	EE	Michel R. C. M. Berkelaar, Jochen A. G. Jess: Gate sizing in MOS digital circuits with linear programming. EURO-DAC 1990: 217-221

Coauthor Index

1	Harm Arts	[6] [8]
2	Reinaldo A. Bergamaschi	[3]
3	Daniel Brand	[3]
4	Pim H. W. Buurman	[2] [5]
5	C. A. J. van Eijk	[6] [9]
6	Koen van Eijk	[8] [11]
7	Lukas P. P. P. van Ginneken	[4]
8	E. T. A. F. Jacobs	[10]
9	Jochen A. G. Jess	[1] [2] [5]
10	M. A. J. Kolsteren	[9]
11	Wolfgang Kunz	[12]
12	Ingmar Neumann	[12]
13	S. Prakash	[3]
14	J. W. J. M. Rutten	[7] [9]
15	Dominik Stoffel	[12]
16	Leon Stok	[3]
17	Kolja Sulimma	[12]

Colors in the list of coauthors