2009 |
44 | EE | Anshuman Chandra,
Yasunari Kanzawa,
Rohit Kapur:
Proactive management of X's in scan chains for compression.
ISQED 2009: 260-265 |
2008 |
43 | EE | Anshuman Chandra,
Felix Ng,
Rohit Kapur:
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction.
DATE 2008: 462-467 |
42 | EE | Anshuman Chandra,
Rohit Kapur:
Interval Based X-Masking for Scan Compression Architectures.
ISQED 2008: 821-826 |
41 | EE | Anshuman Chandra,
Rohit Kapur:
Bounded Adjacent Fill for Low Capture Power Scan Testing.
VTS 2008: 131-138 |
40 | EE | Rohit Kapur,
Subhasish Mitra,
Thomas W. Williams:
Historical Perspective on Scan Compression.
IEEE Design & Test of Computers 25(2): 114-120 (2008) |
2007 |
39 | EE | Rajesh Galivanche,
Rohit Kapur,
Antonio Rubio:
Testing in the year 2020.
DATE 2007: 960-965 |
38 | | Maria Gkatziani,
Rohit Kapur,
Qing Su,
Ben Mathew,
Roberto Mattiuzzo,
Laura Tarantini,
Cy Hay,
Salvatore Talluto,
Thomas W. Williams:
Accurately Determining Bridging Defects from Layout.
DDECS 2007: 87-90 |
37 | EE | Peter Wohl,
John A. Waicukauski,
Rohit Kapur,
S. Ramnath,
Emil Gizdarski,
Thomas W. Williams,
P. Jaini:
Minimizing the Impact of Scan Compression.
VTS 2007: 67-74 |
36 | EE | Anshuman Chandra,
Haihua Yan,
Rohit Kapur:
Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction.
VTS 2007: 84-92 |
2004 |
35 | EE | Rohit Kapur:
Security vs. Test Quality: Are they mutually exclusive?.
ITC 2004: 1414 |
34 | EE | Nodari Sitchinava,
Samitha Samaranayake,
Rohit Kapur,
Emil Gizdarski,
Frederic Neuveux,
Thomas W. Williams:
Changing the Scan Enable during Shift.
VTS 2004: 73-78 |
2003 |
33 | EE | Nahmsuk Oh,
Rohit Kapur,
Thomas W. Williams,
Jim Sproch:
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture.
DATE 2003: 10110-10115 |
32 | EE | Francisco DaSilva,
Yervant Zorian,
Lee Whetsel,
Karim Arabi,
Rohit Kapur:
Overview of the IEEE P1500 Standard.
ITC 2003: 988-997 |
31 | EE | Samitha Samaranayake,
Emil Gizdarski,
Nodari Sitchinava,
Frederic Neuveux,
Rohit Kapur,
Thomas W. Williams:
A Reconfigurable Shared Scan-in Architecture.
VTS 2003: 9-14 |
30 | EE | Bruce D. Cory,
Rohit Kapur,
Bill Underwood:
Speed Binning with Path Delay Test in 150-nm Technology.
IEEE Design & Test of Computers 20(5): 41-45 (2003) |
2002 |
29 | EE | Rohit Kapur,
Thomas W. Williams:
Manufacturing Test of SoCs.
Asian Test Symposium 2002: 317-319 |
28 | EE | Jing-Jia Liou,
Li-C. Wang,
Kwang-Ting Cheng,
Jennifer Dworak,
M. Ray Mercer,
Rohit Kapur,
Thomas W. Williams:
Enhancing test efficiency for delay fault testing using multiple-clocked schemes.
DAC 2002: 371-374 |
27 | EE | Rohit Kapur,
Thomas W. Williams,
M. Ray Mercer:
Directed-Binary Search in Logic BIST Diagnostics.
DATE 2002: 1121 |
26 | EE | Nahmsuk Oh,
Rohit Kapur,
Thomas W. Williams:
Fast seed computation for reseeding shift register in test pattern compression.
ICCAD 2002: 76-81 |
25 | EE | Jing-Jia Liou,
Li-C. Wang,
Kwang-Ting Cheng,
Jennifer Dworak,
M. Ray Mercer,
Rohit Kapur,
Thomas W. Williams:
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.
ITC 2002: 407-416 |
24 | EE | Loïs Guiller,
Frederic Neuveux,
S. Duggirala,
R. Chandramouli,
Rohit Kapur:
Integrating DFT in the Physical Synthesis Flow.
ITC 2002: 788-795 |
23 | EE | Samitha Samaranayake,
Nodari Sitchinava,
Rohit Kapur,
Minesh B. Amin,
Thomas W. Williams:
Dynamic Scan: Driving Down the Cost of Test.
IEEE Computer 35(10): 63-68 (2002) |
22 | EE | Erik Jan Marinissen,
Rohit Kapur,
Maurice Lousberg,
Teresa L. McLaurin,
Mike Ricchetti,
Yervant Zorian:
On IEEE P1500's Standard for Embedded Core Test.
J. Electronic Testing 18(4-5): 365-383 (2002) |
2001 |
21 | | Rohit Kapur,
Maurice Lousberg,
Tony Taylor,
Brion L. Keller,
Paul Reuter,
Douglas Kay:
CTL the language for describing core-based test.
ITC 2001: 131-139 |
20 | | Rohit Kapur,
Thomas W. Williams:
Tester retargetable patterns.
ITC 2001: 721-727 |
19 | | Ajay Khoche,
Rohit Kapur,
David Armstrong,
Thomas W. Williams,
Mick Tegethoff,
Jochen Rivoir:
A new methodology for improved tester utilization.
ITC 2001: 916-923 |
18 | EE | Dwayne Burek,
Garen Darbinyan,
Rohit Kapur,
Maurice Lousberg,
Teresa L. McLaurin,
Mike Ricchetti:
IP and Automation to Support IEEE P1500.
VTS 2001: 411-412 |
17 | EE | Rohit Kapur,
R. Chandramouli,
Thomas W. Williams:
Strategies for Low-Cost Test.
IEEE Design & Test of Computers 18(6): 47-54 (2001) |
2000 |
16 | EE | F. Hayat,
Thomas W. Williams,
Rohit Kapur,
D. Hsu:
DFT closure.
Asian Test Symposium 2000: 8-9 |
15 | EE | Thomas W. Williams,
Rohit Kapur:
Design for Testability in Nanometer Technologies; Searching for Quality.
ISQED 2000: 167-172 |
14 | | Yervant Zorian,
Erik Jan Marinissen,
Rohit Kapur:
On using IEEE P1500 SECT for test plug-n-play.
ITC 2000: 770-777 |
13 | EE | Rohit Kapur,
Cy Hay,
Thomas W. Williams:
The Mutating Metric for Benchmarking Test.
IEEE Design & Test of Computers 17(3): 18-21 (2000) |
1999 |
12 | | Rohit Kapur:
High level ATPG is important and is on its way!
ITC 1999: 1115-1116 |
11 | | Yervant Zorian,
Erik Jan Marinissen,
Rohit Kapur,
Tony Taylor,
Lee Whetsel:
Towards a standard for embedded core test: an example.
ITC 1999: 616-627 |
10 | | Rohit Kapur,
Thomas W. Williams:
Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction.
IEEE Computer 32(11): 42-45 (1999) |
1997 |
9 | EE | Magdy S. Abadir,
Rohit Kapur:
Cost-Driven Ranking of Memory Elements for Partial Intrusion.
IEEE Design & Test of Computers 14(3): 45-50 (1997) |
1996 |
8 | | Thomas W. Williams,
Robert H. Dennard,
Rohit Kapur,
M. Ray Mercer,
Wojciech Maly:
IDDQ Test: Sensitivity Analysis of Scaling.
ITC 1996: 786-792 |
7 | | Rohit Kapur,
Edward F. Miller:
System Test and Reliability: Techniques for Avoiding Failure (Guest Editors' Introduction).
IEEE Computer 29(11): 28-30 (1996) |
6 | EE | Rohit Kapur,
Srinivas Patil,
Thomas J. Snethen,
Thomas W. Williams:
A weighted random pattern test generation system.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 1020-1025 (1996) |
1994 |
5 | | Rohit Kapur,
Srinivas Patil,
Thomas J. Snethen,
Thomas W. Williams:
Design of an Efficient Weighted-Random-Pattern Generation System.
ITC 1994: 491-500 |
1992 |
4 | EE | M. Ray Mercer,
Rohit Kapur,
Don E. Ross:
Functional Approaches to Generating Orderings for Efficient Symbolic Representations.
DAC 1992: 624-627 |
3 | | Rohit Kapur,
Jaehong Park,
M. Ray Mercer:
All Tests for a Fault Are Not Equally Valuable for Defect Detection.
ITC 1992: 762-769 |
2 | | Rohit Kapur,
M. Ray Mercer:
Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes.
IEEE Trans. Computers 41(12): 1580-1588 (1992) |
1991 |
1 | EE | Kenneth M. Butler,
Don E. Ross,
Rohit Kapur,
M. Ray Mercer:
Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams.
DAC 1991: 417-420 |