| 2005 |
|---|
| 10 | EE | Robert B. Reese,
Mitchell A. Thornton,
Cherrice Traver:
A Coarse-Grain Phased Logic CPU.
IEEE Trans. Computers 54(7): 788-799 (2005) |
| 9 | EE | Robert B. Reese,
Mitchell A. Thornton,
Cherrice Traver,
David Hemmendinger:
Early evaluation for performance enhancement in phased logic.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 532-550 (2005) |
| 2004 |
|---|
| 8 | EE | Kenneth Fazel,
Lun Li,
Mitchell A. Thornton,
Robert B. Reese,
Cherrice Traver:
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion.
ACM Great Lakes Symposium on VLSI 2004: 413-416 |
| 2003 |
|---|
| 7 | EE | Robert B. Reese,
Mitchell A. Thornton,
Cherrice Traver:
A Coarse-Grain Phased Logic CPU.
ASYNC 2003: 2-13 |
| 6 | EE | Robert B. Reese,
Mitchell A. Thornton,
Cherrice Traver:
A Fine-Grain Phased Logic CPU.
ISVLSI 2003: 70-79 |
| 2002 |
|---|
| 5 | EE | Mitchell A. Thornton,
Kenneth Fazel,
Robert B. Reese,
Cherrice Traver:
Generalized Early Evaluation in Self-Timed Circuits.
DATE 2002: 255-259 |
| 2001 |
|---|
| 4 | | Robert B. Reese,
Mitchell A. Thornton,
Cherrice Traver:
Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation.
ICCD 2001: 18-23 |
| 1996 |
|---|
| 3 | EE | K. W. Hsu,
Cherrice Traver:
Guest Editorial Introduction to the Special Issue on the 1995 IEEE ASIC Conference.
IEEE Trans. VLSI Syst. 4(3): 305 (1996) |
| 1995 |
|---|
| 2 | EE | Garth Baulch,
David Hemmendinger,
Cherrice Traver:
Analyzing and verifying locally clocked circuits with the concurrency workbench.
Great Lakes Symposium on VLSI 1995: 144-147 |
| 1993 |
|---|
| 1 | | Richard Auletta,
Robert B. Reese,
Cherrice Traver:
A Comparison of Synchronous and Asynchronous FSMD Designs.
ICCD 1993: 178-182 |
