Marc Renaudin

2008
59	EE	Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin: Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98
2007
58	EE	Cedric Koch-Hofer, Marc Renaudin: Timed Asynchronous Circuits Modeling using SystemC. FDL 2007: 110-115
57	EE	Yannick Monnet, Marc Renaudin, Régis Leveugle: Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. IOLTS 2007: 113-120
56	EE	Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet: ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. NOCS 2007: 295-306
55	EE	Sylvain Miermont, Pascal Vivet, Marc Renaudin: A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. PATMOS 2007: 556-565
54	EE	Mischa Dohler, Dominique Barthel, Florence Maraninchi, Laurent Mounier, Stephane Aubert, Christophe Dugas, Aurélien Buhrig, Franck Paugnat, Marc Renaudin, Andrzej Duda, Martin Heusse, Fabrice Valois: The ARESA Project: Facilitating Research, Development and Commercialization of WSNs. SECON 2007: 590-599
53	EE	Julien Goulier, Eric André, Marc Renaudin: A new analytical approach of the impact of jitter on continuous time delta sigma converters. VLSI-SoC 2007: 110-115
52	EE	G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain: DPA on quasi delay insensitive asynchronous circuits: formalization and improvement CoRR abs/0710.3443: (2007)
51	EE	N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin: FPGA Architecture for Multi-Style Asynchronous Logic CoRR abs/0710.4711: (2007)
50	EE	Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon: Parallel Asynchronous Watershed Algorithm-Architecture. IEEE Trans. Parallel Distrib. Syst. 18(1): 44-56 (2007)
49	EE	J. Fragoso, Gilles Sicard, Marc Renaudin: Estimation rapide du couple énergie/délai des circuits asynchrones QDI. Technique et Science Informatiques 26(5): 535-565 (2007)
2006
48	EE	D. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin: AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation. ASYNC 2006: 86-97
47	EE	G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin: Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. CHES 2006: 384-398
46	EE	Yannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel: Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. FDTC 2006: 88-97
45	EE	Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet: Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. IOLTS 2006: 125-130
44	EE	Marc Renaudin, Yannick Monnet: Asynchronous Design: Fault Robustness and Security Characteristics. IOLTS 2006: 92-95
43	EE	Eslam Yahya, Marc Renaudin: QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. PATMOS 2006: 583-592
42	EE	Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin: State-holding in Look-Up Tables: application to asynchronous logic. VLSI-SoC 2006: 12-17
41	EE	Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin: Security evaluation of dual rail logic against DPA attacks. VLSI-SoC 2006: 181-186
40	EE	Yannick Monnet, Marc Renaudin, Régis Leveugle: Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. IEEE Trans. Computers 55(9): 1104-1115 (2006)
39	EE	David Rios-Arambula, Aurélien Buhrig, Gilles Sicard, Marc Renaudin: On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits. J. Low Power Electronics 2(1): 45-55 (2006)
2005
38	EE	Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin: An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. ASYNC 2005: 54-63
37	EE	Yannick Monnet, Marc Renaudin, Régis Leveugle: Asynchronous circuits transient faults sensitivity evaluation. DAC 2005: 863-868
36	EE	N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin: FPGA Architecture for Multi-Style Asynchronous Logic. DATE 2005: 32-33
35	EE	G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain: DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. DATE 2005: 424-429
34		Laurent Fesquet, Marc Renaudin: A Programmable Logic Architecture for Prototyping Clockless Circuits. FPL 2005: 293-298
33		Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin: GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. FPL 2005: 299-304
32	EE	Yannick Monnet, Marc Renaudin, Régis Leveugle: Hardening Techniques against Transient Faults for Asynchronous Circuits. IOLTS 2005: 129-134
31	EE	Emmanuel Allier, Julien Goulier, Gilles Sicard, A. Dezzani, Eric André, Marc Renaudin: A 120nm low power asynchronous ADC. ISLPED 2005: 60-65
30	EE	David Rios-Arambula, Aurélien Buhrig, Marc Renaudin: Power Consumption Reduction Using Dynamic Control of Micro Processor Performance. PATMOS 2005: 10-18
29	EE	Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine: A Method to Design Compact Dual-rail Asynchronous Primitives. PATMOS 2005: 571-580
28		Laurent Fesquet, Jerome Quartana, Marc Renaudin: Asynchronous Systems on Programmable Logic. ReCoSoC 2005: 105-112
27	EE	G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard: Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. VLSI-SoC 2005: 11-24
26	EE	Jerome Quartana, Laurent Fesquet, Marc Renaudin: Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. VLSI-SoC 2005: 195-207
25	EE	Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin: Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. VLSI-SoC 2005: 55-69
2004
24	EE	F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin: Asynchronous FIR Filters: Towards a New Digital Processing Chain. ASYNC 2004: 198-206
23	EE	Marc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain: High Security Smartcards. DATE 2004: 228-233
22	EE	Yannick Monnet, Marc Renaudin, Régis Leveugle: Asynchronous Circuits Sensitivity to Fault Injection. IOLTS 2004: 121-128
21	EE	Kamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin: TAST Profiler and Low Energy Asynchronous Design Methodology. PATMOS 2004: 268-277
20	EE	Dhanistha Panyasak, Gilles Sicard, Marc Renaudin: A current shaping methodology for lowering em disturbances in asynchronous circuits. Microelectronics Journal 35(6): 531-540 (2004)
2003
19	EE	Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin: A New Class of Asynchronous A/D Converters Based on Time Quantization. ASYNC 2003: 196-205
18	EE	Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Sirianni: An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. HICSS 2003: 279
17	EE	João Leonardo Fragoso, Gilles Sicard, Marc Renaudin: Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. PATMOS 2003: 171-180
16	EE	Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin: Statistic Implementation of QDI Asynchronous Primitives. PATMOS 2003: 181-191
15	EE	João Leonardo Fragoso, Gilles Sicard, Marc Renaudin: Automatic Generation of 1-of-M QDI Asynchronous Adders. SBCCI 2003: 149-154
14		Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Sirianni: Validation of asynchronous circuit specifications using IF/CADP. VLSI-SOC 2003: 86-91
2002
13	EE	Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana: High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. DATE 2002: 1090
12	EE	Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland: Implementing Asynchronous Circuits on LUT Based FPGAs. FPL 2002: 36-46
11		Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin: Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. IWLS 2002: 191-196
10	EE	Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin: Dynamic Voltage Scheduling for Real Time Asynchronous Systems. PATMOS 2002: 390-399
9	EE	Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard: Low-Power Asynchronous A/D Conversion. PATMOS 2002: 81-91
2001
8	EE	Christian Piguet, Marc Renaudin, Thierry J.-F. Omnés: Low-power systems on chips (SOCs). DATE 2001: 488
7		Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin: Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC 2001: 313-324
1999
6	EE	Marc Renaudin, Pascal Vivet, Frédéric Robin: A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation. ASYNC 1999: 135-144
1998
5	EE	Marc Renaudin, Pascal Vivet, Frédéric Robin: ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. ASYNC 1998: 22-31
1997
4		Frédéric Robin, Gilles Privat, Marc Renaudin: Asynchronous Relaxation of Morphological Operators: A Joint Algorithm-Architecture Perspective. IJPRAI 11(7): 1085-1094 (1997)
1996
3	EE	Alain Guyot, Marc Renaudin, Bachar El Hassan, Volker Levering: Self timed division and square-root extraction. VLSI Design 1996: 376-381
1995
2		Gilles Privat, Frédéric Robin, Marc Renaudin, Bachar El Hassan: A Fine-Grain Asynchronous VLSI Cellular Array Processor Architecture. ISCAS 1995: 1041-1044
1994
1		Marc Renaudin, Bachar El Hassan: The Design of Fast Asynchronous Adder Structures and their Implementation Using D.C.V.S. Logic. ISCAS 1994: 291-294

Coauthor Index

1	F. Aeschlimann	[24]
2	Emmanuel Allier	[9] [19] [24] [31]
3	Eric André	[31] [53]
4	Stephane Aubert	[54]
5	Arnaud Baixas	[33]
6	Dominique Barthel	[54]
7	Edith Beigné	[38] [48]
8	Taha Beyrouthy	[59]
9	Dominique Borrione	[14] [18]
10	Menouer Boubekeur	[14] [18]
11	G. Fraidy Bouesse	[16] [23] [27] [35] [47] [52]
12	Vivian Brégier	[25]
13	Aurélien Buhrig	[30] [39] [54]
14	D. Caucheteux	[48]
15	Sumanta Chaudhuri	[59]
16	Christophe Clavier	[46]
17	Fabien Clermidy	[38]
18	Alain Clouard	[38]
19	Pierre-Yves Coulon	[50]
20	Elisabeth Crochon	[48]
21	Jean-Luc Danger	[59]
22	A. Dezzani	[31]
23	Mischa Dohler	[54]
24	H. Dubreuil	[36] [51]
25	Anh Vu Dihn Duc	[11]
26	Andrzej Duda	[54]
27	Christophe Dugas	[54]
28	Emil Dumitrescu	[18]
29	Sophie Dumont	[35] [52]
30	Laurent Fesquet	[7] [9] [10] [11] [12] [13] [19] [24] [25] [26] [28] [33] [34] [36] [42] [51] [59]
31	Nathalie Feyt	[45]
32	Bertrand Folco	[25] [42]
33	J. Fragoso	[49]
34	João Leonardo Fragoso	[15] [17]
35	Bruno Galilée	[50]
36	Fabien Germain	[23] [35] [52]
37	Julien Goulier	[31] [53]
38	Sylvain Guilley	[59]
39	Alain Guyot	[3]
40	Bachar El Hassan	[1] [2] [3]
41	Martin Heusse	[54]
42	Quoc Thai Ho	[12]
43	Philippe Hoogvorst	[59]
44	N. Huot	[36] [51]
45	Cedric Koch-Hofer	[56] [58]
46	Volker Levering	[3]
47	Régis Leveugle	[22] [32] [37] [40] [45] [46] [57]
48	Franck Mamalet	[50]
49	Florence Maraninchi	[54]
50	Philippe Maurine	[16] [29] [41]
51	Sylvain Miermont	[55]
52	Pascal Moitrel	[45] [46]
53	Yannick Monnet	[22] [32] [37] [40] [44] [45] [46] [57]
54	Laurent Mounier	[14] [54]
55	F. M'Buwa Nzenguet	[45]
56	Thierry J.-F. Omnés	[8]
57	Dhanistha Panyasak	[20]
58	Franck Paugnat	[54]
59	Christian Piguet	[8]
60	Gilles Privat	[2] [4]
61	Ph. Proust	[23]
62	Jerome Quartana	[7] [13] [26] [28] [33]
63	Alin Razafindraibe	[29] [41] [59]
64	Yann Rémond	[21]
65	Salim Renane	[33]
66	Jean-Baptiste Rigaud	[7] [12] [13] [16] [18]
67	David Rios-Arambula	[30] [39]
68	Michel Robert	[29] [41]
69	Frédéric Robin	[2] [4] [5] [6]
70	Robin Rolland	[12]
71	Mohammed Es Salhiene	[10]
72	Gilles Sicard	[9] [15] [16] [17] [19] [20] [21] [27] [31] [39] [47] [49]
73	Antoine Sirianni	[14] [18]
74	Kamel Slimani	[21]
75	Laurent Sourgen	[23]
76	M. Steiner	[42]
77	Yvain Thonnart	[56]
78	J. P. Tual	[23]
79	Fabrice Valois	[54]
80	Pascal Vivet	[5] [6] [38] [55] [56]
81	Eslam Yahya	[43]

Colors in the list of coauthors