| 2004 |
|---|
| 62 | EE | Jennifer Dworak,
Brad Cobb,
James Wingfield,
M. Ray Mercer:
Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects.
DATE 2004: 1066-1071 |
| 61 | EE | Jennifer Dworak,
James Wingfield,
M. Ray Mercer:
A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects.
DFT 2004: 460-468 |
| 60 | EE | Jennifer Dworak,
David Dorsey,
Amy Wang,
M. Ray Mercer:
Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets.
VTS 2004: 9-15 |
| 2003 |
|---|
| 59 | EE | Yuxin Tian,
Michael R. Grimaila,
Weiping Shi,
M. Ray Mercer:
Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method.
Asian Test Symposium 2003: 354-359 |
| 58 | EE | James Wingfield,
Jennifer Dworak,
M. Ray Mercer:
Function-Based Dynamic Compaction and its Impact on Test Set Sizes.
DFT 2003: 167-174 |
| 57 | EE | Li-C. Wang,
Angela Krstic,
Leonard Lee,
Kwang-Ting Cheng,
M. Ray Mercer,
Thomas W. Williams,
Magdy S. Abadir:
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.
ITC 2003: 1041-1050 |
| 2002 |
|---|
| 56 | EE | Jing-Jia Liou,
Li-C. Wang,
Kwang-Ting Cheng,
Jennifer Dworak,
M. Ray Mercer,
Rohit Kapur,
Thomas W. Williams:
Enhancing test efficiency for delay fault testing using multiple-clocked schemes.
DAC 2002: 371-374 |
| 55 | EE | Rohit Kapur,
Thomas W. Williams,
M. Ray Mercer:
Directed-Binary Search in Logic BIST Diagnostics.
DATE 2002: 1121 |
| 54 | EE | Sooryong Lee,
Brad Cobb,
Jennifer Dworak,
Michael R. Grimaila,
M. Ray Mercer:
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults.
DATE 2002: 94-101 |
| 53 | EE | Jennifer Dworak,
James Wingfield,
Brad Cobb,
Sooryong Lee,
Li-C. Wang,
M. Ray Mercer:
Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults.
DFT 2002: 177-185 |
| 52 | EE | Jing-Jia Liou,
Li-C. Wang,
Kwang-Ting Cheng,
Jennifer Dworak,
M. Ray Mercer,
Rohit Kapur,
Thomas W. Williams:
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.
ITC 2002: 407-416 |
| 2001 |
|---|
| 51 | EE | Jennifer Dworak,
Jason D. Wicker,
Sooryong Lee,
Michael R. Grimaila,
M. Ray Mercer,
Kenneth M. Butler,
Bret Stewart,
Li-C. Wang:
Defect-Oriented Testing and Defective-Part-Level Prediction.
IEEE Design & Test of Computers 18(1): 31-41 (2001) |
| 2000 |
|---|
| 50 | EE | Jennifer Dworak,
Michael R. Grimaila,
Brad Cobb,
Ting-Chi Wang,
Li-C. Wang,
M. Ray Mercer:
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.
Asian Test Symposium 2000: 151- |
| 49 | | Jennifer Dworak,
Michael R. Grimaila,
Sooryong Lee,
Li-C. Wang,
M. Ray Mercer:
Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D.
ITC 2000: 930-939 |
| 1999 |
|---|
| 48 | EE | Ronald W. Mehler,
M. Ray Mercer:
Multi-Level Logic Minimization through Fault Dictionary Analysis.
ICCD 1999: 315-318 |
| 47 | | Jennifer Dworak,
Michael R. Grimaila,
Sooryong Lee,
Li-C. Wang,
M. Ray Mercer:
Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies.
ITC 1999: 1031-1037 |
| 46 | EE | Michael R. Grimaila,
Sooryong Lee,
Jennifer Dworak,
Kenneth M. Butler,
Bret Stewart,
Hari Balachandran,
Bryan Houchins,
Vineet Mathur,
Jaehong Park,
Li-C. Wang,
M. Ray Mercer:
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen.
VTS 1999: 268-274 |
| 1996 |
|---|
| 45 | EE | Li-C. Wang,
M. Ray Mercer,
Thomas W. Williams:
A Better ATPG Algorithm and Its Design Principles.
ICCD 1996: 248-253 |
| 44 | EE | Jaehong Park,
M. Ray Mercer:
Using Functional Information and Strategy Switching in Sequential ATPG.
ICCD 1996: 254-260 |
| 43 | | Li-C. Wang,
M. Ray Mercer,
Thomas W. Williams:
Using Target Faults To Detect Non-Tartget Defects.
ITC 1996: 629-638 |
| 42 | | Thomas W. Williams,
Robert H. Dennard,
Rohit Kapur,
M. Ray Mercer,
Wojciech Maly:
IDDQ Test: Sensitivity Analysis of Scaling.
ITC 1996: 786-792 |
| 41 | EE | Chanhee Oh,
M. Ray Mercer:
Efficient logic-level timing analysis using constraint-guided critical path search.
IEEE Trans. VLSI Syst. 4(3): 346-355 (1996) |
| 1995 |
|---|
| 40 | | Li-C. Wang,
M. Ray Mercer,
Thomas W. Williams:
On Efficiently and Reliably Achieving Low Defective Part Levels.
ITC 1995: 616-625 |
| 39 | EE | Li-C. Wang,
M. Ray Mercer,
Sophia W. Kao,
Thomas W. Williams:
On the decline of testing efficiency as fault coverage approaches 100%.
VTS 1995: 74-83 |
| 1994 |
|---|
| 38 | | Ronn B. Brashear,
Noel Menezes,
Chanhee Oh,
Lawrence T. Pillage,
M. Ray Mercer:
Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis.
EDAC-ETC-EUROASIC 1994: 332-337 |
| 37 | | Mark A. Heap,
M. Ray Mercer:
Least Upper Bounds an OBDD Sizes.
IEEE Trans. Computers 43(6): 764-767 (1994) |
| 1993 |
|---|
| 36 | | Jaehong Park,
M. Ray Mercer:
An Efficient Symbolic Design Verification System.
ICCD 1993: 294-298 |
| 35 | | Eun Sei Park,
M. Ray Mercer:
Switch-Level ATPG Using Constraint-Guided Line Justification.
ITC 1993: 616-625 |
| 1992 |
|---|
| 34 | EE | M. Ray Mercer,
Rohit Kapur,
Don E. Ross:
Functional Approaches to Generating Orderings for Efficient Symbolic Representations.
DAC 1992: 624-627 |
| 33 | EE | Ronn B. Brashear,
Douglas R. Holberg,
M. Ray Mercer,
Lawrence T. Pillage:
ETA: electrical-level timing analysis.
ICCAD 1992: 258-262 |
| 32 | | Mark A. Heap,
William A. Rogers,
M. Ray Mercer:
A Synthesis Algorithm for Two-Level XOR Based Circuits.
ICCD 1992: 459-463 |
| 31 | | Rohit Kapur,
Jaehong Park,
M. Ray Mercer:
All Tests for a Fault Are Not Equally Valuable for Defect Detection.
ITC 1992: 762-769 |
| 30 | | Rohit Kapur,
M. Ray Mercer:
Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes.
IEEE Trans. Computers 41(12): 1580-1588 (1992) |
| 29 | | Eun Sei Park,
M. Ray Mercer,
Thomas W. Williams:
The Total Delay Fault Model and Statistical Delay Fault Coverage.
IEEE Trans. Computers 41(6): 688-698 (1992) |
| 28 | EE | Eun Sei Park,
M. Ray Mercer:
An efficient delay test generation system for combinational logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(7): 926-938 (1992) |
| 1991 |
|---|
| 27 | EE | Kenneth M. Butler,
Don E. Ross,
Rohit Kapur,
M. Ray Mercer:
Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams.
DAC 1991: 417-420 |
| 26 | EE | Thomas W. Williams,
Bill Underwood,
M. Ray Mercer:
The Interdependence Between Delay-Optimization of Synthesized Networks and Testing.
DAC 1991: 87-92 |
| 25 | | Eun Sei Park,
Bill Underwood,
Thomas W. Williams,
M. Ray Mercer:
Delay Testing Quality in Timing-Optimized Designs.
ITC 1991: 897-905 |
| 24 | | M. Ray Mercer:
Testing and Design Verification of Electronic Components.
IEEE Computer 24(9): 107-108 (1991) |
| 23 | EE | Don E. Ross,
Kenneth M. Butler,
M. Ray Mercer:
Exact ordered binary decision diagram size when representing classes of symmetric functions.
J. Electronic Testing 2(3): 243-259 (1991) |
| 1990 |
|---|
| 22 | EE | Eun Sei Park,
M. Ray Mercer:
An Efficient Delay Test Generation System for Combinational Logic Circuits.
DAC 1990: 522-528 |
| 21 | EE | Kenneth M. Butler,
M. Ray Mercer:
The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design.
DAC 1990: 673-678 |
| 20 | | M. Ray Mercer:
Guest Editorial: ITC 20th Anniversary.
IEEE Design & Test of Computers 7(2): 2-3 (1990) |
| 1989 |
|---|
| 19 | EE | C. Thomas Glover,
M. Ray Mercer:
A Deterministic Approach to Adjacency Testing for Delay Faults.
DAC 1989: 351-356 |
| 1988 |
|---|
| 18 | EE | Rhonda Kay Gaede,
Don E. Ross,
M. Ray Mercer,
Kenneth M. Butler:
CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology.
DAC 1988: 597-600 |
| 17 | EE | C. Thomas Glover,
M. Ray Mercer:
A Method of Delay Fault Test Generation.
DAC 1988: 90-95 |
| 16 | | Eun Sei Park,
Thomas W. Williams,
M. Ray Mercer:
Statistical Delay Fault Coverage and Defect Level for Delay Faults.
ITC 1988: 492-499 |
| 15 | | Steven P. Smith,
Bill Underwood,
M. Ray Mercer:
D^3FS: A Demand Driven Deductive Fault Simulator.
ITC 1988: 582-592 |
| 1987 |
|---|
| 14 | EE | Steven P. Smith,
M. Ray Mercer,
B. Brodk:
Demand Driven Simulation: BACKSIM.
DAC 1987: 181-187 |
| 13 | EE | Tom E. Kirkland,
M. Ray Mercer:
A Topological Search Algorithm for ATPG.
DAC 1987: 502-508 |
| 1986 |
|---|
| 12 | | Tom E. Kirkland,
M. Ray Mercer:
A Two-Level Guidance Heuristic for ATPG.
FJCC 1986: 841-846 |
| 11 | | Ki Soo Hwang,
M. Ray Mercer:
Informed Test Generation Guidance Using Partially Specified Fanout Constraints.
ITC 1986: 113-120 |
| 10 | | M. Ray Mercer:
Logic Elements for Universally Testable Circuits.
ITC 1986: 493-497 |
| 9 | | Rhonda Kay Gaede,
M. Ray Mercer,
Bill Underwood:
Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm.
ITC 1986: 498-505 |
| 8 | | Vishwani D. Agrawal,
M. Ray Mercer:
Deterministic Versus Random Testing.
ITC 1986: 718 |
| 7 | EE | Ki Soo Hwang,
M. Ray Mercer:
Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 564-572 (1986) |
| 1985 |
|---|
| 6 | EE | Eric Schell,
M. Ray Mercer:
CADTOOLS: a CAD algorithm development system.
DAC 1985: 658-666 |
| 5 | | John Salick,
Bill Underwood,
M. Ray Mercer:
Built-In Self Test Input Generator for Programmable Logic Arrays.
ITC 1985: 115-125 |
| 1984 |
|---|
| 4 | | Bill Underwood,
M. Ray Mercer:
Correlating Testability with Fault Detection.
ITC 1984: 697-704 |
| 1983 |
|---|
| 3 | | M. Ray Mercer:
Testing Issues at the University of Texas.
ITC 1983: 158-159 |
| 1982 |
|---|
| 2 | | Vishwani D. Agrawal,
M. Ray Mercer:
Testability Measures : What Do They Tell Us ?
ITC 1982: 391-399 |
| 1981 |
|---|
| 1 | | M. Ray Mercer,
Vishwani D. Agrawal,
Carlos M. Roman:
Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation.
ITC 1981: 561-565 |
