2008 |
34 | EE | Tae-Hyoung Kim,
Jason Liu,
John Keane,
Chris H. Kim:
Circuit techniques for ultra-low power subthreshold SRAMs.
ISCAS 2008: 2574-2577 |
33 | EE | Dong Jiao,
Jie Gu,
Pulkit Jain,
Chris H. Kim:
Enhancing beneficial jitter using phase-shifted clock distribution.
ISLPED 2008: 21-26 |
32 | EE | Pulkit Jain,
Tae-Hyoung Kim,
John Keane,
Chris H. Kim:
A multi-story power delivery technique for 3D integrated circuits.
ISLPED 2008: 57-62 |
31 | EE | Jie Gu,
John Keane,
Sachin S. Sapatnekar,
Chris H. Kim:
Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property.
IEEE Trans. VLSI Syst. 16(2): 206-209 (2008) |
30 | EE | Sanjay V. Kumar,
Chris H. Kim,
Sachin S. Sapatnekar:
Body Bias Voltage Computations for Process and Temperature Compensation.
IEEE Trans. VLSI Syst. 16(3): 249-262 (2008) |
29 | EE | Jonggab Kil,
Jie Gu,
Chris H. Kim:
A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting.
IEEE Trans. VLSI Syst. 16(4): 456-465 (2008) |
28 | EE | John Keane,
Hanyong Eom,
Tae-Hyoung Kim,
Sachin S. Sapatnekar,
Chris H. Kim:
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits.
IEEE Trans. VLSI Syst. 16(5): 598-602 (2008) |
2007 |
27 | EE | Paulo F. Butzen,
André Inácio Reis,
Chris H. Kim,
Renato P. Ribas:
Modeling and estimating leakage current in series-parallel CMOS networks.
ACM Great Lakes Symposium on VLSI 2007: 269-274 |
26 | EE | Sanjay V. Kumar,
Chris H. Kim,
Sachin S. Sapatnekar:
NBTI-Aware Synthesis of Digital Circuits.
DAC 2007: 370-375 |
25 | EE | Jie Gu,
Sachin S. Sapatnekar,
Chris H. Kim:
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift.
DAC 2007: 87-92 |
24 | EE | John Keane,
Tae-Hyoung Kim,
Chris H. Kim:
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation.
ISLPED 2007: 189-194 |
23 | EE | Jie Gu,
Hanyong Eom,
Chris H. Kim:
Sleep transistor sizing and control for resonant supply noise damping.
ISLPED 2007: 80-85 |
22 | EE | Paulo F. Butzen,
André Inácio Reis,
Chris H. Kim,
Renato P. Ribas:
Modeling Subthreshold Leakage Current in General Transistor Networks.
ISVLSI 2007: 512-513 |
21 | EE | Paulo F. Butzen,
André Inácio Reis,
Chris H. Kim,
Renato P. Ribas:
Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates.
PATMOS 2007: 474-484 |
20 | EE | Tae-Hyoung Kim,
John Keane,
Hanyong Eom,
Chris H. Kim:
Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design.
IEEE Trans. VLSI Syst. 15(7): 821-829 (2007) |
2006 |
19 | EE | Sanjay V. Kumar,
Chris H. Kim,
Sachin S. Sapatnekar:
Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems.
ASP-DAC 2006: 559-564 |
18 | EE | John Keane,
Hanyong Eom,
Tae-Hyoung Kim,
Sachin S. Sapatnekar,
Chris H. Kim:
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing.
DAC 2006: 425-428 |
17 | EE | Sanjay V. Kumar,
Chris H. Kim,
Sachin S. Sapatnekar:
An analytical model for negative bias temperature instability.
ICCAD 2006: 493-496 |
16 | EE | Tae-Hyoung Kim,
Hanyong Eom,
John Keane,
Chris H. Kim:
Utilizing reverse short channel effect for optimal subthreshold circuit design.
ISLPED 2006: 127-130 |
15 | EE | Jie Gu,
John Keane,
Chris H. Kim:
Modeling and analysis of leakage induced damping effect in low voltage LSIs.
ISLPED 2006: 382-387 |
14 | EE | Jonggab Kil,
Jie Gu,
Chris H. Kim:
A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting.
ISLPED 2006: 67-72 |
13 | EE | Sanjay V. Kumar,
Chris H. Kim,
Sachin S. Sapatnekar:
Impact of NBTI on SRAM Read Stability and Design for Reliability.
ISQED 2006: 210-218 |
12 | EE | Amit Agarwal,
Saibal Mukhopadhyay,
Arijit Raychowdhury,
Kaushik Roy,
Chris H. Kim:
Leakage Power Analysis and Reduction for Nanoscale Circuits.
IEEE Micro 26(2): 68-80 (2006) |
11 | EE | Chris H. Kim,
Kaushik Roy,
Steven Hsu,
Ram Krishnamurthy,
Shekhar Borkar:
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits.
IEEE Trans. VLSI Syst. 14(6): 646-649 (2006) |
2005 |
10 | EE | Chris H. Kim,
Steven Hsu,
Ram Krishnamurthy,
Shekhar Borkar,
Kaushik Roy:
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems.
IOLTS 2005: 100-105 |
9 | EE | Jie Gu,
Chris H. Kim:
Multi-story power delivery for supply noise reduction and low voltage operation.
ISLPED 2005: 192-197 |
8 | EE | Kee-Jong Kim,
Chris H. Kim,
Kaushik Roy:
TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique.
ISQED 2005: 59-64 |
7 | EE | Chris H. Kim,
Jae-Joon Kim,
Saibal Mukhopadhyay,
Kaushik Roy:
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations.
IEEE Trans. VLSI Syst. 13(3): 349-357 (2005) |
2004 |
6 | EE | Amit Agarwal,
Chris H. Kim,
Saibal Mukhopadhyay,
Kaushik Roy:
Leakage in nano-scale technologies: mechanisms, impact and design considerations.
DAC 2004: 6-11 |
5 | EE | Hari Ananthan,
Chris H. Kim,
Kaushik Roy:
Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS.
ISLPED 2004: 8-13 |
2003 |
4 | EE | Chris H. Kim,
Jae-Joon Kim,
Saibal Mukhopadhyay,
Kaushik Roy:
A forward body-biased low-leakage SRAM cache: device and architecture considerations.
ISLPED 2003: 6-9 |
3 | EE | Saibal Mukhopadhyay,
Cassondra Neau,
R. T. Cakici,
Amit Agarwal,
Chris H. Kim,
Kaushik Roy:
Gate leakage reduction for scaled devices using transistor stacking.
IEEE Trans. VLSI Syst. 11(4): 716-730 (2003) |
2002 |
2 | EE | Chris H. Kim,
Kaushik Roy:
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction.
DATE 2002: 163-167 |
1 | EE | Chris H. Kim,
Kaushik Roy:
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors.
ISLPED 2002: 251-254 |