Alex Orailoglu

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168EEMingjing Chen, Alex Orailoglu: Deflecting crosstalk by routing reconsideration through refined signal correlation estimation. ACM Great Lakes Symposium on VLSI 2009: 369-374
167EEChengmo Yang, Alex Orailoglu: A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization. CASES 2008: 11-20
166EEKwangyoon Lee, Alex Orailoglu: Application specific non-volatile primary memory for embedded systems. CODES+ISSS 2008: 31-36
165EEGaro Bournoutian, Alex Orailoglu: Miss reduction in embedded processors through dynamic, power-friendly cache design. DAC 2008: 304-309
164EEWenjing Rao, Alex Orailoglu: Towards fault tolerant parallel prefix adders in nanoelectronic systems. DATE 2008: 360-365
163EEMingjing Chen, Alex Orailoglu: Test cost minimization through adaptive test development. ICCD 2008: 234-239
162EEKwangyoon Lee, Alex Orailoglu: Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems. SASP 2008: 69-74
161EEFawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara: Scheduling Power-Constrained Tests through the SoC Functional Bus. IEICE Transactions 91-D(3): 736-746 (2008)
160EEFawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara: Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. ASP-DAC 2007: 720-725
159EEChengmo Yang, Alex Orailoglu: Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs. CASES 2007: 150-154
158EEChengmo Yang, Alex Orailoglu: Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules. CODES+ISSS 2007: 15-20
157EEWenjing Rao, Alex Orailoglu, Ramesh Karri: Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs. DATE 2007: 865-869
156EEWenjing Rao, Alex Orailoglu, Ramesh Karri: Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays. DSN 2007: 216-224
155EERaid Ayoub, Alex Orailoglu: Power efficient register file update approach for embedded processors. ICCD 2007: 431-437
154EEMingjing Chen, Alex Orailoglu: Circuit-level mismatch modelling and yield optimization for CMOS analog circuits. ICCD 2007: 526-532
153EER. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram: Architectures for Silicon Nanoelectronics and Beyond. IEEE Computer 40(1): 25-33 (2007)
152EEYiorgos Makris, Alex Orailoglu: On the identification of modular test requirements for low cost hierarchical test path construction. Integration 40(3): 315-325 (2007)
151EEPeter Petrov, Alex Orailoglu: Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory. International Journal of Parallel Programming 35(2): 157-177 (2007)
150EEWenjing Rao, Alex Orailoglu, Ramesh Karri: Towards Nanoelectronics Processor Architectures. J. Electronic Testing 23(2-3): 235-254 (2007)
149EEChengmo Yang, Alex Orailoglu: Power efficient branch prediction through early identification of branch addresses. CASES 2006: 169-178
148EEWenjing Rao, Alex Orailoglu, Ramesh Karri: Topology aware mapping of logic functions onto nanowire-based crossbar architectures. DAC 2006: 723-726
147EEWenjing Rao, Alex Orailoglu, Ramesh Karri: Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. European Test Symposium 2006: 63-68
146EEFawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara: Power-Constrained SOC Test Schedules through Utilization of Functional Buses. ICCD 2006
145EEChengmo Yang, Alex Orailoglu: Power-efficient instruction delivery through trace reuse. PACT 2006: 192-201
144EEWenjing Rao, Alex Orailoglu, Ramesh Karri: Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance. VTS 2006: 214-221
143EEMingjing Chen, Hosam Haggag, Alex Orailoglu: Decision Tree Based Mismatch Diagnosis in Analog Circuits. VTS 2006: 278-285
142 Carlos Galup-Montoro, Sergio Bampi, Alex Orailoglu: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005 ACM 2005
141EETongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu: Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. ASP-DAC 2005: 1192-1195
140EERasit Onur Topaloglu, Alex Orailoglu: Forward discrete probability propagation method for device performance characterization under process variations. ASP-DAC 2005: 220-223
139EEWenjing Rao, Alex Orailoglu, Ramesh Karri: Fault tolerant nanoelectronic processor architectures. ASP-DAC 2005: 311-316
138EERaid Ayoub, Alex Orailoglu: A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses. ASP-DAC 2005: 729-734
137EEPeter Petrov, Daniel Tracy, Alex Orailoglu: Energy-effcient physically tagged caches for embedded processors with virtual memory. DAC 2005: 17-22
136EERasit Onur Topaloglu, Alex Orailoglu: A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs. DAC 2005: 851-856
135EEWenjing Rao, Alex Orailoglu, Ramesh Karri: Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors. ICCD 2005: 533-542
134EEPeter Petrov, Alex Orailoglu: A reprogrammable customization framework for efficient branch resolution in embedded processors. ACM Trans. Embedded Comput. Syst. 4(2): 452-468 (2005)
133EEIsmet Bayraktaroglu, Alex Orailoglu: The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations. IEEE Trans. Computers 54(1): 61-75 (2005)
132EEOzgur Sinanoglu, Alex Orailoglu: Test power reductions through computationally efficient, decoupled scan chain modifications. IEEE Transactions on Reliability 54(2): 215-223 (2005)
131EEOzgur Sinanoglu, Alex Orailoglu: Efficient RT-Level Fault Diagnosis. J. Comput. Sci. Technol. 20(2): 166-174 (2005)
130 Alex Orailoglu, Pai H. Chou, Petru Eles, Axel Jantsch: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004 ACM 2004
129EEOzgur Sinanoglu, Alex Orailoglu: Efficient RT-level fault diagnosis methodology. ASP-DAC 2004: 212-217
128EERasit Onur Topaloglu, Alex Orailoglu: On mismatch in the deep sub-micron era - from physics to circuits. ASP-DAC 2004: 62-67
127EEBaris Arslan, Alex Orailoglu: CircularScan: A Scan Architecture for Test Cost Reduction. DATE 2004: 1290-1295
126EEOzgur Sinanoglu, Alex Orailoglu: Scan Power Minimization through Stimulus and Response Transformations. DATE 2004: 404-409
125EEWenjing Rao, Alex Orailoglu, G. Su: Frugal linear network-based test decompression for drastic test cost reductions. ICCAD 2004: 721-725
124EEBaris Arslan, Alex Orailoglu: Design space exploration for aggressive test cost reduction in CircularScan architectures. ICCAD 2004: 726-731
123EEBaris Arslan, Ozgur Sinanoglu, Alex Orailoglu: Extending the Applicability of Parallel-Serial Scan Designs. ICCD 2004: 200-203
122EESule Ozev, Alex Orailoglu: End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths. ICCD 2004: 72-77
121EEOzgur Sinanoglu, Alex Orailoglu: Autonomous Yet Deterministic Test of SOC Cores. ITC 2004: 1359-1368
120EEWenjing Rao, Alex Orailoglu, Ramesh Karri: Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems. ITC 2004: 472-478
119EEBaris Arslan, Alex Orailoglu: Test Cost Reduction Through A Reconfigurable Scan Architecture. ITC 2004: 945-952
118EESule Ozev, Ismet Bayraktaroglu, Alex Orailoglu: Seamless Test of Digital Components in Mixed-Signal Paths. IEEE Design & Test of Computers 21(1): 44-55 (2004)
117EEPeter Petrov, Alex Orailoglu: Transforming Binary Code for Low-Power Embedded Processors. IEEE Micro 24(3): 21-33 (2004)
116EESule Ozev, Alex Orailoglu: Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead. IEEE Trans. VLSI Syst. 12(7): 756-765 (2004)
115EEPeter Petrov, Alex Orailoglu: Low-power instruction bus encoding for embedded processors. IEEE Trans. VLSI Syst. 12(8): 812-826 (2004)
114EEPeter Petrov, Alex Orailoglu: Tag compression for low power in dynamically customizable embedded processors. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1031-1047 (2004)
113EEYiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu: Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test. IEEE Transactions on Reliability 53(2): 269-278 (2004)
112EEÉrika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu: Searching for Global Test Costs Optimization in Core-Based Systems. J. Electronic Testing 20(4): 357-373 (2004)
111EEOzgur Sinanoglu, Alex Orailoglu: Fast and energy-frugal deterministic test through efficient compression and compaction techniques. Journal of Systems Architecture 50(5): 257-266 (2004)
110 Rajesh Gupta, Yukihiro Nakamura, Alex Orailoglu, Pai H. Chou: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003 ACM 2003
109EEOzgur Sinanoglu, Alex Orailoglu: Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test. Asian Test Symposium 2003: 202-209
108EEBaris Arslan, Alex Orailoglu: Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information. Asian Test Symposium 2003: 230-235
107EEWenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu: Test application time and volume compression through seed overlapping. DAC 2003: 732-737
106EEPeter Petrov, Alex Orailoglu: Power Efficiency through Application-Specific Instruction Memory Transformations. DATE 2003: 10030-10035
105EEWenjing Rao, Alex Orailoglu: Virtual Compression through Test Vector Stitching for Scan Based Designs. DATE 2003: 10104-10109
104EEPeter Petrov, Alex Orailoglu: Low-power Branch Target Buffer for Application-Specific Embedded Processors. DSD 2003: 158-165
103EEOzgur Sinanoglu, Alex Orailoglu: Hierarchical Constraint Conscious RT-level Test Generation. DSD 2003: 312-318
102EEPeter Petrov, Alex Orailoglu: Customizable Embedded Processor Architectures. DSD 2003: 468-475
101EEPeter Petrov, Alex Orailoglu: Compiler-Based Register Name Adjustment for Low-Power Embedded Processors. ICCAD 2003: 523-528
100EEOzgur Sinanoglu, Alex Orailoglu: Partial Core Encryption for Performance-Efficient Test of SOCs. ICCAD 2003: 91-94
99EEPeter Petrov, Alex Orailoglu: Virtual Page Tag Reduction for Low-power TLBs. ICCD 2003: 371-374
98EEOzgur Sinanoglu, Alex Orailoglu: Aggressive Test Power Reduction Through Test Stimuli Transformation. ICCD 2003: 542-547
97EEOzgur Sinanoglu, Alex Orailoglu: Modeling Scan Chain Modifications For Scan-in Test Power Minimization. ITC 2003: 602-611
96EEIsmet Bayraktaroglu, Alex Orailoglu: Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression. VTS 2003: 113-120
95EEPeter Petrov, Alex Orailoglu: Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors. IEEE Design & Test of Computers 20(1): 18-25 (2003)
94 Alex Orailoglu, Alexander V. Veidenbaum: Guest Editors' Introduction: Application-Specific Microprocessors. IEEE Design & Test of Computers 20(1): 6-7 (2003)
93EEOzgur Sinanoglu, Alex Orailoglu: Compacting Test Responses for Deeply Embedded SoC Cores. IEEE Design & Test of Computers 20(4): 22-30 (2003)
92EEIsmet Bayraktaroglu, Alex Orailoglu: Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs. IEEE Trans. Computers 52(11): 1480-1489 (2003)
91EEAlex Orailoglu: Guest Editor's Introduction. International Journal of Parallel Programming 31(6): 407-409 (2003)
90EESule Ozev, Alex Orailoglu: Statistical Tolerance Analysis for Assured Analog Test Coverage. J. Electronic Testing 19(2): 173-182 (2003)
89EEOzgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu: Reducing Average and Peak Test Power Through Scan Chain Modification. J. Electronic Testing 19(4): 457-467 (2003)
88EEYiorgos Makris, Alex Orailoglu: Test Requirement Analysis for Low Cost Hierarchical Test Path Construction. Asian Test Symposium 2002: 134-139
87EEPeter Petrov, Alex Orailoglu: Energy frugal tags in reprogrammable I-caches for application-specific embedded processors. CODES 2002: 181-186
86EEPeter Petrov, Alex Orailoglu: Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches. DATE 2002: 1065-1071
85EEIsmet Bayraktaroglu, Alex Orailoglu: Gate Level Fault Diagnosis in Scan-Based BIST. DATE 2002: 376-381
84EESherief Reda, Alex Orailoglu: Reducing Test Application Time Through Test Data Mutation Encoding. DATE 2002: 387-395
83EEÉrika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu: Test Planning and Design Space Exploration in a Core-Based Environment. DATE 2002: 478-485
82EEOzgur Sinanoglu, Alex Orailoglu: Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation. DFT 2002: 325-333
81EEOzgur Sinanoglu, Alex Orailoglu: A novel scan architecture for power-efficient, rapid test. ICCAD 2002: 299-303
80EESule Ozev, Alex Orailoglu: Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits. ICCD 2002: 258-264
79EEBaris Arslan, Alex Orailoglu: Fault Dictionary Size Reduction through Test Response Superposition. ICCD 2002: 480-
78EESule Ozev, Alex Orailoglu, Hosam Haggag: Automated test development and test time reduction for RF subsystems. ISCAS (1) 2002: 581-584
77EESule Ozev, Alex Orailoglu: An Integrated Tool for Analog Test Generation and Fault Simulation. ISQED 2002: 267-272
76EESherief Reda, Rolf Drechsler, Alex Orailoglu: On the Relation between SAT and BDDs for Equivalence Checking. ISQED 2002: 394-399
75EEAlex Orailoglu, Peter Petrov: Low-Power Data Memory Communication for Application-Specific Embedded Processors. ISSS 2002: 219-224
74EEOzgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu: Scan Power Reduction Through Test Data Transition Frequency Analysis. ITC 2002: 844-850
73EEOzgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu: Test Power Reduction through Minimization of Scan Chain Transitions. VTS 2002: 166-172
72EESule Ozev, Alex Orailoglu: Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis. VTS 2002: 213-222
71EELaurence Goodby, Alex Orailoglu, Paul M. Chau: Microarchitectural synthesis of performance-constrained, low-power VLSI designs. ACM Trans. Design Autom. Electr. Syst. 7(1): 122-136 (2002)
70EEIsmet Bayraktaroglu, Alex Orailoglu: Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST. IEEE Design & Test of Computers 19(1): 42-53 (2002)
69EESule Ozev, Christian Olgaard, Alex Orailoglu: Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers. IEEE Design & Test of Computers 19(5): 82-91 (2002)
68EEOzgur Sinanoglu, Alex Orailoglu: Efficient Construction of Aliasing-Free Compaction Circuitry. IEEE Micro 22(5): 82-92 (2002)
67EEYiorgos Makris, Jamison Collins, Alex Orailoglu: Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface. J. Electronic Testing 18(1): 29-42 (2002)
66EEOzgur Sinanoglu, Alex Orailoglu: Compaction Schemes with Minimum Test Application Time. Asian Test Symposium 2001: 199-204
65EESobeeh Almukhaizim, Peter Petrov, Alex Orailoglu: Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit. Asian Test Symposium 2001: 319-324
64EEIsmet Bayraktaroglu, Alex Orailoglu: Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck? Asian Test Symposium 2001: 373-378
63EEPeter Petrov, Alex Orailoglu: Towards effective embedded processors in codesigns: customizable partitioned caches. CODES 2001: 79-84
62EEIsmet Bayraktaroglu, Alex Orailoglu: Test Volume and Application Time Reduction Through Scan Chain Concealment. DAC 2001: 151-155
61EEPeter Petrov, Alex Orailoglu: Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors. DAC 2001: 512-517
60EEIsmet Bayraktaroglu, Alex Orailoglu: Diagnosis for scan-based BIST: reaching deep into the signatures. DATE 2001: 102-111
59 Peter Petrov, Alex Orailoglu: Data cache energy minimizations through programmable tag size matching to the applications. ISSS 2001: 113-117
58 Ozgur Sinanoglu, Alex Orailoglu: Space and time compaction schemes for embedded cores. ITC 2001: 521-529
57 Christian Olgaard, Sule Ozev, Alex Orailoglu: Testability implications in low-cost integrated radio transceivers: a Bluetooth case study. ITC 2001: 965-974
56EEOzgur Sinanoglu, Alex Orailoglu: RT-level Fault Simulation Based on Symbolic Propagation. VTS 2001: 240-245
55EEYiorgos Makris, Vishal Patel, Alex Orailoglu: Efficient Transparency Extraction and Utilization in Hierarchical Test. VTS 2001: 246-251
54EEPeter Petrov, Alex Orailoglu: Performance and power effectiveness in embedded processors customizable partitioned caches. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1309-1318 (2001)
53EEIsmet Bayraktaroglu, Alex Orailoglu: Concurrent test for digital linear systems. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1132-1142 (2001)
52EEYiorgos Makris, Jamison Collins, Alex Orailoglu: Fast hierarchical test path construction for DFT-free controller-datapath circuits. Asian Test Symposium 2000: 185-190
51EEIsmet Bayraktaroglu, Alex Orailoglu: Accumulation-based concurrent fault detection for linear digital state variable systems. Asian Test Symposium 2000: 484-
50EEIsmet Bayraktaroglu, Alex Orailoglu: Improved fault diagnosis in scan-based BIST via superposition. DAC 2000: 55-58
49EESule Ozev, Ismet Bayraktaroglu, Alex Orailoglu: Test Synthesis for Mixed-Signal SOC Paths. DATE 2000: 128-133
48EELaurence Goodby, Alex Orailoglu: Test Quality and Fault Risk in Digital Filter Datapath BIST. DATE 2000: 468-475
47 Ismet Bayraktaroglu, Alex Orailoglu: Deterministic partitioning techniques for fault diagnosis in scan-based BIST. ITC 2000: 273-282
46EESule Ozev, Alex Orailoglu: Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems. VTS 2000: 149-156
45EEYiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu: Invariance-Based On-Line Test for RTL Controller-Datapath Circuits. VTS 2000: 459-464
44EESamuel Norman Hamilton, Alex Orailoglu: On-line test for fault-secure fault identification. IEEE Trans. VLSI Syst. 8(4): 446-452 (2000)
43EEYiorgos Makris, Alex Orailoglu: Channel-Based Behavioral Test Synthesis for Improved Module Reachability. DATE 1999: 283-288
42EESamuel Norman Hamilton, Alex Orailoglu, Andre Hertwig: Self Recovering Controller and Datapath Codesign. DATE 1999: 596-601
41EESule Ozev, Alex Orailoglu: Low-Cost Test for Large Analog IC's. DFT 1999: 101-
40EEYiorgos Makris, Alex Orailoglu: A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths. DFT 1999: 339-347
39EEIsmet Bayraktaroglu, Alex Orailoglu: Low-Cost On-Line Test for Digital Filters. VTS 1999: 446-451
38EELaurence Goodby, Alex Orailoglu: Redundancy and testability in digital filter datapaths. IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 631-644 (1999)
37EEIsmet Bayraktaroglu, K. Udawatta, Alex Orailoglu: An Examination of PRPG Selection Approaches for Large, Industrial Designs. Asian Test Symposium 1998: 440-
36EESamuel Norman Hamilton, Alex Orailoglu: Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs. DATE 1998: 604-
35EESamuel Norman Hamilton, Alex Orailoglu: Transient and Intermittent Fault Recovery without Rollback. DFT 1998: 252-260
34EEAlex Orailoglu: Graceful Degradation in Synthesis of VLSI ICs. DFT 1998: 301-311
33EEYiorgos Makris, Alex Orailoglu: DFT guidance through RTL test justification and propagation analysis. ITC 1998: 668-
32EESamuel Norman Hamilton, Alex Orailoglu: Efficient Self-Recovering ASIC Design. IEEE Design & Test of Computers 15(4): 25-35 (1998)
31EEAlex Orailoglu: On-Line Fault Resilience Through Gracefully Degradable ASICs. J. Electronic Testing 12(1-2): 145-151 (1998)
30EEYiorgos Makris, Alex Orailoglu: RTL Test Justification and Propagation Analysis for Modular Designs. J. Electronic Testing 13(2): 105-120 (1998)
29EELaurence Goodby, Alex Orailoglu: Frequency-Domain Compatibility in Digital Filter BIST. DAC 1997: 540-545
28 Samuel Norman Hamilton, Alex Orailoglu: Microarchitectural Synthesis of ICs with Embedded Concurrent Fault Isolation. FTCS 1997: 329-338
27EEAlex Orailoglu: Microarchitectural synthesis for rapid BIST testing. IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 573-586 (1997)
26EELaurence Goodby, Alex Orailoglu: Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths. DAC 1996: 813-818
25EEAlex Orailoglu: Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs. ICCD 1996: 112-117
24EER. L. Campbell, P. Kuekes, David Y. Lepejian, W. Maly, Michael Nicolaidis, Alex Orailoglu: Can Defect-Tolerant Chips Better Meet the Quality Challenge? VTS 1996: 362-363
23EERamesh Karri, Karin Högstedt, Alex Orailoglu: Computer-Aided Design of Fault-Tolerant VLSI Systems. IEEE Design & Test of Computers 13(3): 88-96 (1996)
22 Alex Orailoglu, Ramesh Karri: Automatic Synthesis of Self-Recovering VLSI Systems. IEEE Trans. Computers 45(2): 131-142 (1996)
21EEMahsa Vahidi, Alex Orailoglu: Metric-based transformations for self testable VLSI designs with high test concurrency. EURO-DAC 1995: 136-141
20 Laurence Goodby, Alex Orailoglu: Towards 100% Testable FIR Digital Filters. ITC 1995: 394-402
19EEMahsa Vahidi, Alex Orailoglu: Testability metrics for synthesis of self-testable designs and effective test plans. VTS 1995: 170-175
18EEIan G. Harris, Alex Orailoglu: Microarchitectural Synthesis of VLSI Designs with High Test Concurrency. DAC 1994: 206-211
17EERamesh Karri, Alex Orailoglu: Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis. DAC 1994: 552-556
16 Ian G. Harris, Alex Orailoglu: Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST. EDAC-ETC-EUROASIC 1994: 119-123
15 Ian G. Harris, Alex Orailoglu: SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability. ICCD 1994: 101-104
14 Laurence Goodby, Alex Orailoglu, Paul M. Chau: Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs. ICCD 1994: 323-326
13 Karin Högstedt, Alex Orailoglu: Integrating Binding Constraints in the Synthesis of Area-Efficient Self-Recovering Microarchitectures. ICCD 1994: 331-334
12EEAlex Orailoglu, Ramesh Karri: Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures. IEEE Trans. VLSI Syst. 2(3): 304-311 (1994)
11EEAlex Orailoglu, Ramesh Karri: Synthesis of fault-tolerant and real-time microarchitectures. Journal of Systems and Software 25(1): 73-84 (1994)
10EERamesh Karri, Alex Orailoglu: High-Level Synthesis of Fault-Secure Microarchitectures. DAC 1993: 429-433
9 Ramesh Karri, Alex Orailoglu: Optimal Self-Recovering Microarchitecture Synthesis. FTCS 1993: 512-521
8 Alex Orailoglu, Ian G. Harris: Test Path Generation and Test Scheduling for Self-Testable Designs. ICCD 1993: 528-531
7 Ian G. Harris, Alex Orailoglu: Intertwined Scheduling, Module Selection and Allocation in Time-and-Area. ISCAS 1993: 1682-1685
6EERamesh Karri, Alex Orailoglu: Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs. DAC 1992: 662-665
5 Ramesh Karri, Alex Orailoglu: Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs. FTCS 1992: 519-526
4 Alex Orailoglu, Ramesh Karri: High-Level Synthesis of Self-Recovering MicroArchitectures. ICCD 1992: 286-289
3EERamesh Karri, Alex Orailoglu: ALPS: An Algorithm for Pipeline Data Path Synthesis. MICRO 1991: 124-132
2EEAmir K. Hekmatpour, Alex Orailoglu, Paul M. Chau: Hierarchical Modeling of the VLSI Design Process. IEEE Expert 6(2): 56-70 (1991)
1EEAlex Orailoglu, Daniel Gajski: Flow graph representation. DAC 1986: 503-509

Coauthor Index

1Sobeeh Almukhaizim [65]
2Baris Arslan [79] [108] [119] [123] [124] [127]
3Raid Ayoub [138] [155]
4R. Iris Bahar [153]
5Sergio Bampi [142]
6Ismet Bayraktaroglu [37] [39] [45] [47] [49] [50] [51] [53] [60] [62] [64] [70] [73] [74] [85] [89] [92] [96] [107] [113] [118] [133]
7Garo Bournoutian [165]
8R. L. Campbell [24]
9Luigi Carro [83] [112]
10Paul M. Chau [2] [14] [71]
11Mingjing Chen [143] [154] [163] [168]
12Pai H. Chou [110] [130]
13Jamison Collins [52] [67]
14Érika F. Cota [83] [112]
15Rolf Drechsler [76]
16Petru Eles [130]
17Hideo Fujiwara [146] [160] [161]
18Daniel Gajski (Daniel D. Gajski) [1]
19Carlos Galup-Montoro [142]
20Laurence Goodby [14] [20] [26] [29] [38] [48] [71]
21Rajesh K. Gupta (Rajesh Gupta) [110]
22Hosam Haggag [78] [143]
23Samuel Norman Hamilton [28] [32] [35] [36] [42] [44]
24Dan W. Hammerstrom [153]
25Justin E. Harlow III [153]
26Ian G. Harris [7] [8] [15] [16] [18]
27Amir K. Hekmatpour [2]
28Andre Hertwig [42]
29Karin Högstedt [13] [23]
30Fawnizu Azmadi Hussin [146] [160] [161]
31Axel Jantsch [130]
32William H. Joyner Jr. [153]
33Ramesh Karri [3] [4] [5] [6] [9] [10] [11] [12] [17] [22] [23] [120] [135] [139] [141] [144] [147] [148] [150] [156] [157]
34P. Kuekes [24]
35Clifford Lau [153]
36Kwangyoon Lee [162] [166]
37David Y. Lepejian [24]
38Marcelo Lubaszewski [83] [112]
39Yiorgos Makris [30] [33] [40] [43] [45] [52] [55] [67] [88] [113] [152]
40W. Maly [24]
41Diana Marculescu [153]
42Yukihiro Nakamura [110]
43Michael Nicolaidis [24]
44Christian Olgaard [57] [69]
45Sule Ozev [41] [46] [49] [57] [69] [72] [77] [78] [80] [90] [116] [118] [122]
46Vishal Patel [55]
47Massoud Pedram [153]
48Peter Petrov [54] [59] [61] [63] [65] [75] [86] [87] [95] [99] [101] [102] [104] [106] [114] [115] [117] [134] [137] [151]
49Wenjing Rao [105] [107] [120] [125] [135] [139] [144] [147] [148] [150] [156] [157] [164]
50Sherief Reda [76] [84]
51Ozgur Sinanoglu [56] [58] [66] [68] [73] [74] [81] [82] [89] [93] [97] [98] [100] [103] [109] [111] [121] [123] [126] [129] [131] [132]
52G. Su [125]
53Rasit Onur Topaloglu [128] [136] [140]
54Daniel Tracy [137]
55K. Udawatta [37]
56Mahsa Vahidi [19] [21]
57Alexander V. Veidenbaum [94]
58Tongquan Wei [141]
59Kaijie Wu [141]
60Chengmo Yang [145] [149] [158] [159] [167]
61Tomokazu Yoneda [146] [160] [161]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)