Raimund Ubar

2008
54	EE	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Parallel fault backtracing for calculation of fault coverage. ASP-DAC 2008: 667-672
53	EE	Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee: Code Coverage Analysis using High-Level Decision Diagrams. DDECS 2008: 201-206
52	EE	Eero Ivask, Jaan Raik, Raimund Ubar: Web-Based Framework for Parallel Distributed Test. DDECS 2008: 271-274
51	EE	Artur Jutman, Anton Tsertov, Raimund Ubar: Calculation of LFSR Seed and Polynomial Pair for BIST Applications. DDECS 2008: 275-278
50	EE	Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee: Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA 2008: 222-227
49	EE	Eero Ivask, Jaan Raik, Raimund Ubar: Distributed Approach for Genetic Test Generation in the Field of Digital Electronics. IDC 2008: 127-136
48	EE	Jaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin: Mixed hierarchical-functional fault models for targeting sequential cores. Journal of Systems Architecture - Embedded Systems Design 54(3-4): 465-477 (2008)
47	EE	Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar: Hybrid BIST optimization using reseeding and test set compaction. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 254-262 (2008)
46	EE	Raimund Ubar, Sergei Kostin, Jaan Raik: Embedded fault diagnosis in digital systems with BIST. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 279-287 (2008)
2007
45		Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski: Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS 2007: 35-40
44	EE	Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar: Hybrid BIST Optimization Using Reseeding and Test Set Compaction. DSD 2007: 596-603
43	EE	Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evartson, Harri Lensen: Fault Diagnosis in Integrated Circuits with BIST. DSD 2007: 604-610
42	EE	Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus: Hierarchical Identification of Untestable Faults in Sequential Circuits. DSD 2007: 668-671
41	EE	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. European Test Symposium 2007: 131-136
40	EE	Jaan Raik, Raimund Ubar, Vineeth Govind: Test Configurations for Diagnosing Faulty Links in NoC Switches. European Test Symposium 2007: 29-34
39	EE	Gert Jervan, Helena Kruus, Elmet Orasson, Raimund Ubar: Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems. SIES 2007: 71-77
2006
38		Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubatova, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jiri Bucek: Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006 IEEE Computer Society 2006
37	EE	Jaan Raik, Raimund Ubar, Taavi Viilukas: High-Level Decision Diagram based Fault Models for Targeting FSMs. DSD 2006: 353-358
36	EE	Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng: Off-Line Testing of Delay Faults in NoC Interconnects. DSD 2006: 677-680
35	EE	Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin: Test Time Minimization for Hybrid BIST of Core-Based Systems. J. Comput. Sci. Technol. 21(6): 907-912 (2006)
2005
34	EE	Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov: An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. DSD 2005: 412-419
33	EE	Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar: Improved Fault Emulation for Synchronous Sequential Circuits. DSD 2005: 72-78
32	EE	Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz: Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. DSD 2005: 79-82
31	EE	Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman: Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. EDCC 2005: 332-344
30	EE	Jaan Raik, Tanel Nõmmeots, Raimund Ubar: A New Testability Calculation Method to Guide RTL Test Generation. J. Electronic Testing 21(1): 71-82 (2005)
2004
29	EE	Raimund Ubar, Maksim Jenihhin: Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting. DELTA 2004: 3-8
28		Eero Ivask, Jaan Raik, Raimund Ubar, André Schneider: Web-Based Environment for Digital Electronics Test Tools. Virtual Enterprises and Collaborative Networks 2004: 435-442
27	EE	Vladimir Hahanov, Raimund Ubar, Subhasish Mitra: Conference Reports. IEEE Design & Test of Computers 21(6): 594-595 (2004)
2003
26	EE	Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin: Test Time Minimization for Hybrid BIST of Core-Based Systems. Asian Test Symposium 2003: 318-325
25	EE	Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin: Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. DFT 2003: 225-
24	EE	Vladimir Hahanov, Raimund Ubar, Stanley Hyduke: Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. DSD 2003: 370-377
23		Vladimir Hahanov, Raimund Ubar: Conference Reports. IEEE Design & Test of Computers 20(6): 103- (2003)
22	EE	Raimund Ubar: Design Error Diagnosis with Re-Synthesis in Combinational Circuits. J. Electronic Testing 19(1): 73-82 (2003)
2002
21	EE	André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová: Internet-Based Collaborative Test Generation with MOSCITO. DATE 2002: 221-226
20	EE	Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik: Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. DELTA 2002: 86-91
19	EE	André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng: Integrated Design and Test Generation Under Internet Based Environment MOSCITO. DSD 2002: 187-195
18	EE	Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus: A Hybrid BIST Architecture and Its Optimization for SoC Testing. ISQED 2002: 273-279
17	EE	T. Cibáková, María Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Hierarchical test generation for combinational circuits with real defects coverage. Microelectronics Reliability 42(7): 1141-1149 (2002)
2001
16	EE	Raimund Ubar, Artur Jutman, Zebo Peng: Timing simulation of digital circuits with binary decision diagrams. DATE 2001: 460-466
15	EE	Elmet Orasson, Rein Raidma, Raimund Ubar, Gert Jervan, Zebo Peng: Fast Test Cost Calculation for Hybrid BIST in Digital Systems. DSD 2001: 318-325
14	EE	Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED 2001: 365-371
13	EE	Mykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. Microelectronics Reliability 41(12): 2023-2040 (2001)
2000
12	EE	Adam Morawiec, Raimund Ubar, Jaan Raik: Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. DATE 2000: 743
11	EE	Gert Jervan, Zebo Peng, Raimund Ubar: Test Cost Minimization for Hybrid Bist. DFT 2000: 283-291
10	EE	Raimund Ubar, Jaan Raik: Efficient Hierarchical Approach to Test Generation for Digital Systems. ISQED 2000: 189-196
9	EE	Jaan Raik, Raimund Ubar: Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. J. Electronic Testing 16(3): 213-226 (2000)
1999
8	EE	Raimund Ubar, Jaan Raik, Adam Morawiec: Cycle-based Simulation with Decision Diagrams. DATE 1999: 454-458
7	EE	Jaan Raik, Raimund Ubar: Sequential Circuit Test Generation Using Decision Diagram Models. DATE 1999: 736-740
6		Raimund Ubar, Dominique Borrione: Design Error Diagnosis in Digital Circuits without Error Model. VLSI 1999: 281-292
1997
5	EE	Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar: Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. DFT 1997: 212-217
4	EE	Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Raimund Ubar: A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. ED&TC 1997: 560-565
1996
3		Raimund Ubar, Marina Brik: Multi-Level Test Generation and Fault Diagnosis for Finite State Machines. EDCC 1996: 264-282
2	EE	Raimund Ubar: Test Synthesis with Alternative Graphs. IEEE Design & Test of Computers 13(1): 48-57 (1996)
1994
1		Raimund Ubar: Test Generation for Digital Systems Based on Alternative Graphs. EDCC 1994: 151-164

Coauthor Index

1	Tomas Bengtsson	[36]
2	Alfredo Benso	[4] [5]
3	Mykola Blyzniuk	[13]
4	Dominique Borrione	[6]
5	Marina Brik	[3] [20]
6	Jiri Bucek	[38]
7	T. Cibáková	[17] [21]
8	Sergei Devadze	[31] [41] [50] [54]
9	Karl-Heinz Diener	[19] [21]
10	Petru Eles	[25] [26] [35]
11	Peeter Ellervee	[33] [50] [53]
12	Teet Evartson	[43]
13	María Fischerová	[17]
14	Vineeth Govind	[40]
15	Elena Gramatová	[17] [19] [21]
16	Vladimir Hahanov	[23] [24] [27]
17	Thomas Hollstein	[19]
18	Stanley Hyduke	[24]
19	Eero Ivask	[19] [20] [21] [28] [49] [52]
20	Maksim Jenihhin	[25] [26] [29] [35] [45] [48] [50] [53]
21	Gert Jervan	[11] [15] [18] [25] [26] [35] [39] [44] [47] [50]
22	Artur Jutman	[16] [31] [34] [36] [41] [51] [54]
23	Irena Kazymyra	[13]
24	Sergei Kostin	[43] [46]
25	Zdenek Kotásek	[38]
26	Anna Krivenko	[42]
27	Helena Kruus	[18] [39] [44] [47]
28	Margus Kruus	[42]
29	Pavel Kubalík	[38]
30	Hana Kubatova	[38]
31	Shashi Kumar	[36]
32	Wieslaw Kuzmicz	[13] [14] [17] [19] [32]
33	Harri Lensen	[43]
34	P. Miklos	[21]
35	Subhasish Mitra	[27]
36	Adam Morawiec	[8] [12]
37	Tanel Nõmmeots	[30]
38	Ondrej Novák	[38]
39	Elmet Orasson	[15] [39] [44] [47]
40	Zebo Peng	[11] [15] [16] [18] [19] [25] [26] [35] [36]
41	Witold A. Pleskacz	[13] [14] [17] [32] [45]
42	Paolo Prinetto	[4] [5]
43	Rein Raidma	[15]
44	Jaan Raik	[5] [7] [8] [9] [10] [12] [13] [14] [17] [20] [21] [28] [30] [31] [32] [33] [34] [37] [40] [41] [42] [43] [45] [46] [48] [49] [50] [52] [53] [54]
45	Michal Rakowski	[45]
46	Maurizio Rebaudengo	[4] [5]
47	Uljana Reinsalu	[53]
48	Matteo Sonza Reorda	[4] [5] [38]
49	André Schneider	[19] [21] [28]
50	Bernd Straube	[38]
51	Joachim Sudbrock	[32]
52	Valentin Tihhomirov	[33]
53	Anton Tsertov	[51]
54	Taavi Viilukas	[37] [48]
55	V. Vislogubov	[34]

Colors in the list of coauthors