| 2006 |
|---|
| 11 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
Implicit grading of multiple path delay faults.
ACM Trans. Design Autom. Electr. Syst. 11(2): 346-361 (2006) |
| 2005 |
|---|
| 10 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
Efficient identification of (critical) testable path delay faults using decision diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 77-87 (2005) |
| 2004 |
|---|
| 9 | EE | Mahilchi Milir Vaseekar Kumar,
Saravanan Padmanaban,
Spyros Tragoudas:
Low power ATPG for path delay faults.
ACM Great Lakes Symposium on VLSI 2004: 389-392 |
| 8 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults.
DATE 2004: 50-55 |
| 7 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
An Adaptive Path Delay Fault Diagnosis Methodology.
ISQED 2004: 491-496 |
| 6 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
A Critical Path Selection Method for Delay Testing.
ITC 2004: 232-241 |
| 2003 |
|---|
| 5 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
Non-Enumerative Path Delay Fault Diagnosis .
DATE 2003: 10322-10327 |
| 4 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
An implicit path-delay fault diagnosis methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1399-1408 (2003) |
| 3 | EE | Saravanan Padmanaban,
Maria K. Michael,
Spyros Tragoudas:
Exact path delay fault coverage with fundamental ZBDD operations.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 305-316 (2003) |
| 2002 |
|---|
| 2 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
Exact Grading of Multiple Path Delay Faults.
DATE 2002: 84-88 |
| 2001 |
|---|
| 1 | | Saravanan Padmanaban,
Maria K. Michael,
Spyros Tragoudas:
Exact path delay grading with fundamental BDD operations.
ITC 2001: 642-651 |
