Yoji Kajitani

2008
47	EE	Yoji Kajitani: Floorplan and Placement. Encyclopedia of Algorithms 2008
2007
46	EE	Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani: A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os. IEICE Transactions 90-A(5): 924-931 (2007)
2006
45	EE	Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani: How does partitioning matter for 3D floorplanning? ACM Great Lakes Symposium on VLSI 2006: 73-78
44	EE	Yoji Kajitani: Theory of placement by numDAG related with single-sequence, SP, BSG, and O-tree. ISCAS 2006
43	EE	Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani: Adaptive Porting of Analog IPs with Reusable Conservative Properties. ISVLSI 2006: 18-23
42	EE	Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani: The Oct-Touched Tile: A New Architecture for Shape-Based Routing. IEICE Transactions 89-A(2): 448-455 (2006)
2005
41	EE	Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani: The oct-touched tile: a new architecture for shape-based routing. ACM Great Lakes Symposium on VLSI 2005: 126-129
40	EE	Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani: A new approach based on LFF for optimization of dynamic hardware reconfigurations. ISCAS (2) 2005: 1210-1213
39	EE	Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani: Fixed-outline floorplanning with constraints through instance augmentation. ISCAS (2) 2005: 1883-1886
38	EE	Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi: Equidistance routing in high-speed VLSI layout design. Integration 38(3): 439-449 (2005)
2004
37	EE	Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani: A device-level placement with multi-directional convex clustering. ACM Great Lakes Symposium on VLSI 2004: 196-201
36	EE	Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi: Equidistance routing in high-speed VLSI layout design. ACM Great Lakes Symposium on VLSI 2004: 220-223
35	EE	Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani: Abstraction and optimization of consistent floorplanning with pillar block constraints. ASP-DAC 2004: 19-24
34	EE	Xuliang Zhang, Yoji Kajitani: Space-planning: placement of modules with controlled empty area by single-sequence. ASP-DAC 2004: 25-30
33	EE	Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani: Multi-level placement with circuit schema based clustering in analog IC layouts. ASP-DAC 2004: 406-411
32		Xuliang Zhang, Yoji Kajitani: Theory of T-junction floorplans in terms of single-sequence. ISCAS (5) 2004: 341-344
2002
31	EE	Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita: Chip size estimation based on wiring area. APCCAS (2) 2002: 113-118
30	EE	Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin: An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees. DATE 2002: 61-68
29	EE	Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita: Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. VLSI Design 2002: 467-472
28	EE	Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani: Consistent floorplanning with hierarchical superconstraints. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 42-49 (2002)
2001
27	EE	Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani: Consistent floorplanning with super hierarchical constraints. ISPD 2001: 144-149
2000
26	EE	Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani: Self-reforming routing for stochastic search in VLSI interconnection layout. ASP-DAC 2000: 87-92
25		Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake: Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. VLSI Design 2000: 11
1999
24	EE	Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani: Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. ASP-DAC 1999: 125-
1998
23		Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani: Air-Pressure-Model-Based Fast Algorithms for General Floorplan. ASP-DAC 1998: 563-570
22		Shigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani: Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules. ASP-DAC 1998: 571-576
21	EE	Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani: The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. ICCAD 1998: 267-274
20	EE	Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita: The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. ICCAD 1998: 418-425
19	EE	Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani: Module packing based on the BSG-structure and IC layout applications. IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 519-530 (1998)
18	EE	Magnús M. Halldórsson, Shuichi Ueno, Hiroshi Nakao, Yoji Kajitani: Approximating Steiner trees in graphs with restricted weights. Networks 31(4): 283-292 (1998)
1997
17	EE	Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani: Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. ICCAD 1997: 260-265
16	EE	Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu: Design of minimum and uniform bipartites for optimum connection blocks of FPGA. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1377-1383 (1997)
1996
15	EE	Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani: Module placement on BSG-structure and IC layout applications. ICCAD 1996: 484-491
14	EE	Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani: VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1518-1524 (1996)
1995
13	EE	Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani: Rectangle-packing-based module placement. ICCAD 1995: 472-479
12	EE	Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani: Mixed Searching and Proper-Path-Width. Theor. Comput. Sci. 137(2): 253-268 (1995)
1994
11	EE	Shigetoshi Nakatake, Yoji Kajitani: Channel-driven global routing with consistent placement (extended abstract). ICCAD 1994: 350-355
10		Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu: The Totally-Perfect Bipartite Graph and Its Construction. ISAAC 1994: 541-549
9		Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu: Design of Optimum Totally Perfect Connection-Blocks of FPGA. ISCAS 1994: 221-224
8		Yoji Kajitani, Jun Dong Cho, Majid Sarrafzadeh: New Approximation Results on Graph Matching and related Problems. WG 1994: 343-358
7	EE	Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani: Minimal acyclic forbidden minors for the family of graphs with bounded path-width. Discrete Mathematics 127(1-3): 293-304 (1994)
1993
6		Wayne Wei-Ming Dai, Yoji Kajitani, Yorihiko Hirata: Optimal single hop multiple bus networks. ISCAS 1993: 2541-2544
5	EE	Tadashi Arai, Shuichi Ueno, Yoji Kajitani: Generalization of aTheorem on the Parametric Maximum Flow Problem. Discrete Applied Mathematics 41(1): 69-74 (1993)
1991
4		Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani: Mixed-Searching and Proper-Path-Width. ISA 1991: 61-71
1988
3	EE	Yoji Kajitani, Shuichi Ueno, Hiroshi Miyano: Ordering of the elements of a matroid such that its consecutive w elements are independent. Discrete Mathematics 72(1-3): 187-194 (1988)
2	EE	Shuichi Ueno, Yoji Kajitani, Shin'ya Gotoh: On the nonseparating independent set problem and feedback set problem for graphs with no vertex degree exceeding three. Discrete Mathematics 72(1-3): 355-360 (1988)
1983
1	EE	Yoji Kajitani: Order of Channels for Safe Routing and Optimal Compaction of Routing Area. IEEE Trans. on CAD of Integrated Circuits and Systems 2(4): 293-300 (1983)

Coauthor Index

1	Tadashi Arai	[5]
2	Kengo R. Azegami	[25]
3	Jun Dong Cho	[8]
4	Wayne Wei-Ming Dai	[6]
5	Qing Dong	[45]
6	Sheqin Dong	[39] [40]
7	Ning Fu	[35] [41] [42]
8	Toru Fujimura	[43]
9	Kunihiro Fujiyoshi	[9] [10] [13] [14] [15] [16] [19]
10	Masahiro Furuya	[22]
11	Shin'ya Gotoh	[2]
12	Magnús M. Halldórsson	[18]
13	Yorihiko Hirata	[6]
14	Xianlong Hong	[39] [40]
15	Masato Inagi	[46]
16	Kazunori Inoue	[17]
17	Tomonori Izumi	[23]
18	Liyan Jin	[30]
19	Masahiro Kawakita	[20] [29] [31]
20	Yukiko Kubo	[26] [27] [28] [29] [31] [36] [38]
21	Rong Liu	[39]
22	Hiroshi Miyano	[3]
23	Hiroshi Miyashita	[36] [38]
24	Hiroshi Murata	[13] [14] [15] [19]
25	Yuichi Nakamura (Yuhichi Nakamura)	[46]
26	Hiroshi Nakao	[18]
27	Shigetoshi Nakatake	[11] [13] [14] [15] [19] [20] [21] [22] [25] [26] [27] [28] [29] [31] [33] [35] [37] [41] [42] [43]
28	Hiroshi Niitsu	[9] [10] [16]
29	Takashi Nojima	[33] [37] [43]
30	Koji Okazaki	[43]
31	Nobuto Ono	[43]
32	Keishi Sakanushi	[20] [21] [30]
33	Majid Sarrafzadeh	[8]
34	Atsushi Takahashi	[4] [7] [12] [17] [23] [24] [25]
35	Yasuhiro Takashima	[26] [33] [35] [37] [41] [42] [45] [46]
36	Kazuyuki Tateishi	[36] [38]
37	Shuichi Ueno	[2] [3] [4] [5] [7] [12] [18]
38	Yuliang Wu	[40]
39	Tan Yan	[45]
40	Tomoyuki Yoda	[24]
41	Xuliang Zhang	[32] [34]
42	Zhe Zhou	[40]
43	Xiaoke Zhu	[33]
44	Changwen Zhuang	[30]

Colors in the list of coauthors