| 2006 |
|---|
| 5 | EE | Sunan Tugsinavisut,
Roger Su,
Peter A. Beerel:
High-level Synthesis for Highly Concurrent Hardware Systems.
ACSD 2006: 79-90 |
| 2005 |
|---|
| 4 | EE | Sunan Tugsinavisut,
Youpyo Hong,
Daewook Kim,
Kyeounsoo Kim,
Peter A. Beerel:
Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication.
IEEE Trans. VLSI Syst. 13(4): 448-461 (2005) |
| 2003 |
|---|
| 3 | EE | Sunan Tugsinavisut,
Suwicha Jirayucharoensak,
Peter A. Beerel:
An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication.
ISCAS (5) 2003: 361-364 |
| 2002 |
|---|
| 2 | EE | Sunan Tugsinavisut,
Peter A. Beerel:
Control Circuit Templates for Asynchronous Bundled-Data Pipelines.
DATE 2002: 1098 |
| 1 | EE | Sangyun Kim,
Sunan Tugsinavisut,
Peter A. Beerel:
Reducing probabilistic timed petri nets for asynchronous architectural analysis.
Timing Issues in the Specification and Synthesis of Digital Systems 2002: 140-147 |
