ITC 2003:
Charlotte,
NC,
USA
Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA.
IEEE Computer Society 2003, ISBN 0-7803-8106-8 BibTeX
Plenary
Memory Testing And Diagnosis
- Jean Michel Portal, H. Aziza, Didier Née:
EEPROM Memory: Threshold Voltage Built In Self Diagnosis.
23-28
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- Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang:
Fault Pattern Oriented Defect Diagnosis for Memories.
29-38
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- Derek Wright, Manoj Sachdev:
Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie.
39-47
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Jitter Testing Techniques for > GB/S TX/RX Links
- Masashi Shimanouchi:
Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in Production.
48-57
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- Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Makoto Kurosawa, Hirobumi Musha:
Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements.
58-66
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- Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz:
CMOS Built-In Test Architecture for High-Speed Jitter Measurement.
67-76
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High Yield And Effective Testing And Burn-In
- Thomas S. Barnett, Adit D. Singh:
Relating Yield Models to Burn-In Fall-Out in Time.
77-84
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- Yoshihito Nishizaki, Osamu Nakayama, Chiaki Matsumoto, Yoshitaka Kimura, Toshimi Kobayashi, Hiroyuki Nakamura:
Testing DSM ASIC With Static, \DeltaIDDQ, And Dynamic Test Suite: Implementation And Results.
85-94
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- Oleg Semenov, Arman Vassighi, Manoj Sachdev, Ali Keshavarzi, Charles F. Hawkins:
Burn-in Temperature Projections for Deep Sub-micron Technologies.
95-104
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Crosstalk And Delay Test
Improving Design Validation Coverage
Lecture Series-Board And System Test:
Is PXI The Future of Functional Board Test?
Pushing The Envelope of ATE
ADC Test
- Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell:
A New Methodology For ADC Test Flow Optimization.
201-209
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- Gwenolé Maugard, Carsten Wegener, Tom O'Dwyer, Michael Peter Kennedy:
Method of reducing contactor effect when testing high-precision ADCs.
210-217
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- Le Jin, Kumar L. Parthasarathy, Turker Kuyel, Degang Chen, Randall L. Geiger:
Linearity Testing of Precision Analog-to-Digital Converters Using Stationary Nonlinear Inputs.
218-227
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- Stephen K. Sunter:
Testing High Frequency ADCs and DACs with a Low Frequency Analog Bus.
228-235
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Advances in Testing And Analysis Methods
- Franco Stellari, Peilin Song, Moyra K. McManus, Robert Gauthier, Alan J. Weger, Kiran V. Chatty, Mujahid Muhammad, Pia Sanda:
Optical and Electrical Testing of Latchup in I/O Interface Circuits.
236-245
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- Keneth R. Wilsher:
Designed -in-diagnostics: A new optical method.
246-253
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- Romain Desplats, Felix Beaudoin, Philippe Perdu, Nagamani Nataraj, Ted Lundquist, Ketan Shah:
Fault Localization using Time Resolved Photon Emission and STIL Waveforms.
254-263
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- Jeremy A. Rowlette, Travis M. Eiles:
Critical Timing Analysis in Microprocessors Using Near-IR Laser Assisted Device Alteration (LADA).
264-273
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Novel ATPG Approaches
Advances in Diagnostics
- Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton:
Progressive Bridge Identification.
309-318
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- Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung:
Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault.
319-328
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- Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski:
An Efficient and Effective Methodology on the Multiple Fault Diagnosis.
329-338
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- Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak:
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies.
339-348
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Board And System Test:
Advanced Applications of Boundary-Scan
- YongJoon Kim, DongSub Song, YongSeung Shin, Sunghoon Chun, Sungho Kang:
A New Maximal Diagnosis Algorithm for Bus-structured Systems.
349-357
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- Kevin Melocco, Hina Arora, Paul Setlak, Gary Kunselman, Shazia Mardhani:
A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic.
358-367
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- Kendrick Baker:
Constructive Pattern Generation Heuristic for Meeting SSO Limits.
368
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- Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen:
Optimal Interconnect ATPG Under a Ground-Bounce Constraint.
369-378
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Embedded Memory BIST and Repair
- Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante:
Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores.
379-385
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- Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai:
BIST for Deep Submicron ASIC Memories with High Performance Application.
386-392
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- Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow:
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy.
393-402
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Interface Magic
Test And Verification For Cores And SOCS
Keep Compressing This Test Data!
Low-Power Scan
Lecture Series-Board And System Test:
IEEE 1149.6-A Practical Perspective
Extremely Low-Cost Testers
Application Series-Developing Test Interfaces
Practical Application of IDDQ
Delay Test
Optimizing Efficiency in SOC Testing
Board And System Test:
AC-Interconnect Board Test Techniques
RF Testing
Lecture Series-Introduction to MEMS
Application of IDDX
Logic BIST
Microprocessor Test
Board And System Test:
Advances in Testing Microprocessor Motherboards
Latest Developments in ATE Software
Lecture Series-MEMS Testing
Failure Mechanisms And Test Solutions For DSM ICS
- Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey:
Deformations of IC Structure in Test and Yield Learning.
856-865
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- Bram Kruseman, Stefan van den Oetelaar:
Detection of Resistive Shorts in Deep Sub-micron Technologies.
866-875
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- R. D. (Shawn) Blanton, Kumar N. Dwarakanath, Anirudh B. Shah:
Analyzing the Effectiveness of Multiple-Detect Test Sets.
876-885
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- Martin Omaña, Daniele Rossi, Cecilia Metra:
Novel Transient Fault Hardened Static Latch.
886-892
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Can Concurrent Detection Be Achieved At Low Cost?
Test Economics
Board And System Test:
Testing Multiboard Systems
- Liviu Miclea, Szilárd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto:
Agent Based DBIST/DBISR And Its Web/Wireless Management.
952-960
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- Olivier Caty, Ismet Bayraktaroglu, Amitava Majumdar, Richard Lee, John Bell, Lisa Curhan:
Instruction Based BIST for Board/System Level Test of External Memories and Internconnects.
961-970
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- Hardi Hungar, Tiziana Margaria, Bernhard Steffen:
Test-Based Model Generation For Legacy Systems.
971-980
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- Rakesh N. Joshi, Kenneth L. Williams, Lee Whetsel:
Evolution of IEEE 1149.1 Addressable Shadow Protocol Devices.
981-987
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Lecture Series-P1500 Mergeable Cores
I/O Testing-Probe or Not?
Quality
- Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski:
Impact of Multiple-Detect Test Patterns on Product Quality.
1031-1040
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- Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir:
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.
1041-1050
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- Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker:
Simulating Resistive Bridging and Stuck-At Faults.
1051-1059
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Test Data Compression
At-Speed Testing-New Solutions to Old Problems
Extending IEEE 1149.1 Into The Backplane
Infrastructure IP
Analog Model-Based Testing
Test of Future Integrated Systems
DFT Industrial Case Studies
- Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski:
Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions.
1211-1220
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- Graham Hetherington, Richard Simpson:
Circular BIST testing the digital logic within a high speed Serdes.
1221-1228
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- David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Kim, Anil Sabbavarapu, Talal Jaber, Pete Johnson, Dale March, Greg Parrish:
H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing.
1229-1238
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Interconnect Testing And BIST For FPGAS
Board And System Test:
Other Aspects of Board Test
How (In) Adequate is One-Time Testing?
My DFT Is Better Than Yours... Is Better than None...
RF Test 101:
Defining The Problem,
Finding Solutions
The Confluence of Manufacturing Test And Design Validation
PXI:
A Solution For Board Functional Test?
Future ATE:
Perspectives And Requirements
Diagnosis In Modern Time-To-Volume-The Tip of The Iceberg
Multi-GB/S IC Test Challenges And Solutions
DFM:
The Real 90-NM Hurdle
Testing 3G-Controlled Systems:
A Time to Rejoice or A Time to Feel Pain?
ITC 2002 Best Paper
Copyright © Sat May 16 23:26:45 2009
by Michael Ley (ley@uni-trier.de)
