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Xiaoliang Bai

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2008
16EEHongshen Wang, Shusheng Zhang, Kaixing Zhang, Xiaoliang Bai: A Shape Distributions Retrieval Algorithm of 3D CAD Models Based on Normal Direction. ICYCS 2008: 891-896
2007
15EEXuemei Liu, Shusheng Zhong, Xiaoliang Bai, Xuemei Liu: A Modified SOFM Segmentation Method in Reverse Engineering. SNPD (2) 2007: 570-573
14EEChong Zhao, Xiaoliang Bai, Sujit Dey: Evaluating Transient Error Effects in Digital Nanometer Circuits. IEEE Transactions on Reliability 56(3): 381-391 (2007)
2005
13EEChong Zhao, Sujit Dey, Xiaoliang Bai: Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits. IEEE Design & Test of Computers 22(4): 362-375 (2005)
2004
12EEChong Zhao, Xiaoliang Bai, Sujit Dey: A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits. DAC 2004: 894-899
11EER. Dean Adams, Robert Abbott, Xiaoliang Bai, Dwayne Burek, Eric MacDonald: An Integrated Memory Self Test and EDA Solution. MTDT 2004: 92-95
10EEXiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas: Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1256-1263 (2004)
9EEXiaoliang Bai, Sujit Dey: High-level crosstalk defect Simulation methodology for system-on-chip interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1355-1361 (2004)
2003
8EEXiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas: Noise-Aware Driver Modeling for Nanometer Technology. ISQED 2003: 177-182
7EEXiaoliang Bai, Sujit Dey, Angela Krstic: HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. ITC 2003: 112-121
2002
6EEXiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski: Uncertainty-aware circuit optimization. DAC 2002: 58-63
5EELi Chen, Xiaoliang Bai, Sujit Dey: Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. J. Electronic Testing 18(4-5): 529-538 (2002)
2001
4EELi Chen, Xiaoliang Bai, Sujit Dey: Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. DAC 2001: 317-320
3EEXiaoliang Bai, Sujit Dey: High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. VTS 2001: 169-177
2000
2EEXiaoliang Bai, Sujit Dey, Janusz Rajski: Self-test methodology for at-speed test of crosstalk in chip interconnects. DAC 2000: 619-624
1999
1EEMichael Cuviello, Sujit Dey, Xiaoliang Bai, Yi Zhao: Fault modeling and simulation for crosstalk in system-on-chip interconnects. ICCAD 1999: 297-303

Coauthor Index

1Robert Abbott [11]
2R. Dean Adams [11]
3Dwayne Burek [11]
4Rajit Chandra [8] [10]
5Li Chen [4] [5]
6Michael Cuviello [1]
7Sujit Dey [1] [2] [3] [4] [5] [7] [8] [9] [10] [12] [13] [14]
8Angela Krstic [7]
9Xuemei Liu [15]
10Eric MacDonald [11]
11Janusz Rajski [2]
12P. V. Srinivas [8] [10]
13Philip N. Strenski [6]
14Chandramouli Visweswariah [6]
15Hongshen Wang [16]
16Kaixing Zhang [16]
17Shusheng Zhang [16]
18Chong Zhao [12] [13] [14]
19Yi Zhao [1]
20Shusheng Zhong [15]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)