Xiaoliang Bai

2008
16	EE	Hongshen Wang, Shusheng Zhang, Kaixing Zhang, Xiaoliang Bai: A Shape Distributions Retrieval Algorithm of 3D CAD Models Based on Normal Direction. ICYCS 2008: 891-896
2007
15	EE	Xuemei Liu, Shusheng Zhong, Xiaoliang Bai, Xuemei Liu: A Modified SOFM Segmentation Method in Reverse Engineering. SNPD (2) 2007: 570-573
14	EE	Chong Zhao, Xiaoliang Bai, Sujit Dey: Evaluating Transient Error Effects in Digital Nanometer Circuits. IEEE Transactions on Reliability 56(3): 381-391 (2007)
2005
13	EE	Chong Zhao, Sujit Dey, Xiaoliang Bai: Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits. IEEE Design & Test of Computers 22(4): 362-375 (2005)
2004
12	EE	Chong Zhao, Xiaoliang Bai, Sujit Dey: A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits. DAC 2004: 894-899
11	EE	R. Dean Adams, Robert Abbott, Xiaoliang Bai, Dwayne Burek, Eric MacDonald: An Integrated Memory Self Test and EDA Solution. MTDT 2004: 92-95
10	EE	Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas: Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1256-1263 (2004)
9	EE	Xiaoliang Bai, Sujit Dey: High-level crosstalk defect Simulation methodology for system-on-chip interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1355-1361 (2004)
2003
8	EE	Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas: Noise-Aware Driver Modeling for Nanometer Technology. ISQED 2003: 177-182
7	EE	Xiaoliang Bai, Sujit Dey, Angela Krstic: HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. ITC 2003: 112-121
2002
6	EE	Xiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski: Uncertainty-aware circuit optimization. DAC 2002: 58-63
5	EE	Li Chen, Xiaoliang Bai, Sujit Dey: Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. J. Electronic Testing 18(4-5): 529-538 (2002)
2001
4	EE	Li Chen, Xiaoliang Bai, Sujit Dey: Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. DAC 2001: 317-320
3	EE	Xiaoliang Bai, Sujit Dey: High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. VTS 2001: 169-177
2000
2	EE	Xiaoliang Bai, Sujit Dey, Janusz Rajski: Self-test methodology for at-speed test of crosstalk in chip interconnects. DAC 2000: 619-624
1999
1	EE	Michael Cuviello, Sujit Dey, Xiaoliang Bai, Yi Zhao: Fault modeling and simulation for crosstalk in system-on-chip interconnects. ICCAD 1999: 297-303

Coauthor Index

1	Robert Abbott	[11]
2	R. Dean Adams	[11]
3	Dwayne Burek	[11]
4	Rajit Chandra	[8] [10]
5	Li Chen	[4] [5]
6	Michael Cuviello	[1]
7	Sujit Dey	[1] [2] [3] [4] [5] [7] [8] [9] [10] [12] [13] [14]
8	Angela Krstic	[7]
9	Xuemei Liu	[15]
10	Eric MacDonald	[11]
11	Janusz Rajski	[2]
12	P. V. Srinivas	[8] [10]
13	Philip N. Strenski	[6]
14	Chandramouli Visweswariah	[6]
15	Hongshen Wang	[16]
16	Kaixing Zhang	[16]
17	Shusheng Zhang	[16]
18	Chong Zhao	[12] [13] [14]
19	Yi Zhao	[1]
20	Shusheng Zhong	[15]

Colors in the list of coauthors