| 2008 |
|---|
| 82 | EE | Francesco Abate,
Massimo Violante:
Coping with Obsolescence of Processor Cores in Critical Applications.
DFT 2008: 24-32 |
| 81 | EE | Cristiana Bolchini,
Antonio Miele,
Fabio Rebaudengo,
Fabio Salice,
Donatella Sciuto,
Luca Sterpone,
Massimo Violante:
Software and Hardware Techniques for SEU Detection in IP Processors.
J. Electronic Testing 24(1-3): 35-44 (2008) |
| 80 | EE | Eduardo Luis Rhod,
Carlos Arthur Lang Lisbôa,
Luigi Carro,
Matteo Sonza Reorda,
Massimo Violante:
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs.
J. Electronic Testing 24(1-3): 45-56 (2008) |
| 2007 |
|---|
| 79 | EE | Luca Sterpone,
Massimo Violante:
A new decompression system for the configuration process of SRAM-based FPGAS.
ACM Great Lakes Symposium on VLSI 2007: 241-246 |
| 78 | EE | Luca Sterpone,
Massimo Violante:
A new hardware architecture for performing the gridding of DNA microarray images.
ACM Great Lakes Symposium on VLSI 2007: 341-346 |
| 77 | EE | Andrea Manuzzato,
Paolo Rech,
Simone Gerardin,
Alessandro Paccagnella,
Luca Sterpone,
Massimo Violante:
Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs.
DFT 2007: 79-86 |
| 76 | EE | Salvatore Pontarelli,
Luca Sterpone,
Gian-Carlo Cardarilli,
Marco Re,
Matteo Sonza Reorda,
Adelio Salsano,
Massimo Violante:
Optimization of Self Checking FIR filters by means of Fault Injection Analysis.
DFT 2007: 96-104 |
| 75 | EE | Luca Sterpone,
Massimo Violante:
Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs.
European Test Symposium 2007: 159-164 |
| 74 | EE | Salvatore Pontarelli,
Luca Sterpone,
Gian-Carlo Cardarilli,
Marco Re,
Matteo Sonza Reorda,
Adelio Salsano,
Massimo Violante:
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders.
IOLTS 2007: 194-196 |
| 73 | EE | Luca Sterpone,
Matteo Sonza Reorda,
Massimo Violante,
Fernanda Lima Kastensmidt,
Luigi Carro:
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.
J. Electronic Testing 23(1): 47-54 (2007) |
| 2006 |
|---|
| 72 | EE | Maurizio Martina,
Guido Masera,
Andrea Molino,
Fabrizio Vacca,
Luca Sterpone,
Massimo Violante:
A new approach to compress the configuration information of programmable devices.
DATE Designers' Forum 2006: 48-51 |
| 71 | | Luca Sterpone,
Massimo Violante:
ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications.
DDECS 2006: 54-58 |
| 70 | EE | Maurizio Rebaudengo,
Luca Sterpone,
Massimo Violante,
Cristiana Bolchini,
Antonio Miele,
Donatella Sciuto:
Combined software and hardware techniques for the design of reliable IP processors.
DFT 2006: 265-273 |
| 69 | EE | Carlos Arthur Lang Lisbôa,
Luigi Carro,
Matteo Sonza Reorda,
Massimo Violante:
Online hardening of programs against SEUs and SETs.
DFT 2006: 280-290 |
| 68 | EE | Matteo Sonza Reorda,
Luca Sterpone,
Massimo Violante,
Marta Portela-García,
Celia López-Ongil,
Luis Entrena:
Fault Injection-based Reliability Evaluation of SoPCs.
European Test Symposium 2006: 75-82 |
| 67 | EE | Luca Sterpone,
Massimo Violante:
Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices.
IOLTS 2006: 189-190 |
| 66 | EE | Matteo Sonza Reorda,
Massimo Violante:
Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems.
IOLTS 2006: 229-234 |
| 65 | EE | Paolo Bernardi,
Leticia Maria Veiras Bolzani,
Alberto Manzone,
Marcella Guagliumi Massimo Osella,
Massimo Violante,
Matteo Sonza Reorda:
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications.
MTV 2006: 3-8 |
| 64 | EE | Julio Pérez Acle,
Matteo Sonza Reorda,
Massimo Violante:
Early, Accurate Dependability Analysis of CAN-Based Networked Systems.
IEEE Design & Test of Computers 23(1): 38-45 (2006) |
| 63 | EE | Paolo Bernardi,
Leticia Maria Veiras Bolzani,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Fabian Vargas,
Massimo Violante:
A New Hybrid Fault Detection Technique for Systems-on-a-Chip.
IEEE Trans. Computers 55(2): 185-198 (2006) |
| 62 | EE | Luca Sterpone,
Massimo Violante:
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs.
IEEE Trans. Computers 55(6): 732-744 (2006) |
| 61 | EE | Luca Sterpone,
Massimo Violante:
Hardening FPGA-based Systems Against SEUs: A New Design Methodology.
JCP 1(1): 22-30 (2006) |
| 2005 |
|---|
| 60 | EE | Luca Sterpone,
Massimo Violante:
A design flow for protecting FPGA-based systems against single event upsets.
DFT 2005: 436-444 |
| 59 | EE | Paolo Bernardi,
Leticia Maria Veiras Bolzani,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors.
DFT 2005: 445-453 |
| 58 | EE | Paolo Bernardi,
Leticia Maria Veiras Bolzani,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Fabian Vargas,
Massimo Violante:
On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core.
DSN 2005: 50-58 |
| 57 | EE | Ernesto Sánchez,
Massimiliano Schillaci,
Matteo Sonza Reorda,
Giovanni Squillero,
Luca Sterpone,
Massimo Violante:
New evolutionary techniques for test-program generation for complex microprocessor cores.
GECCO 2005: 2193-2194 |
| 56 | EE | Matteo Sonza Reorda,
Luca Sterpone,
Massimo Violante:
Efficient Estimation of SEU Effects in SRAM-Based FPGAs.
IOLTS 2005: 54-59 |
| 55 | EE | Ernesto Sánchez,
Matteo Sonza Reorda,
Giovanni Squillero,
Massimo Violante:
Automatic generation of test sets for SBST of microprocessor IP cores.
SBCCI 2005: 74-79 |
| 2004 |
|---|
| 54 | EE | O. Goloubeva,
Matteo Sonza Reorda,
Massimo Violante:
Automatic Generation of Validation Stimuli for Application-Specific Processors.
DATE 2004: 188-193 |
| 53 | EE | M. Bellato,
Paolo Bernardi,
D. Bortolato,
A. Candelori,
M. Ceschia,
Alessandro Paccagnella,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante,
P. Zambolin:
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA.
DATE 2004: 584-589 |
| 52 | EE | Matteo Sonza Reorda,
Massimo Violante:
On-Line Analysis and Perturbation of CAN Networks.
DFT 2004: 424-432 |
| 51 | EE | Ernesto Sánchez,
Giovanni Squillero,
Massimo Violante:
Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems.
EvoWorkshops 2004: 230-239 |
| 50 | EE | Paolo Bernardi,
Matteo Sonza Reorda,
Luca Sterpone,
Massimo Violante:
On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs.
IOLTS 2004: 115-120 |
| 49 | EE | Leticia Maria Veiras Bolzani,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Fabian Vargas,
Massimo Violante:
Hybrid Soft Error Detection by Means of Infrastructure IP Cores.
IOLTS 2004: 79-88 |
| 48 | EE | Fulvio Corno,
Julio Pérez Acle,
Matteo Sonza Reorda,
Massimo Violante:
A multi-level approach to the dependability analysis of networked systems based on the CAN protocol.
SBCCI 2004: 71-75 |
| 47 | EE | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
A New Approach to Software-Implemented Fault Tolerance.
J. Electronic Testing 20(4): 433-437 (2004) |
| 46 | EE | Matteo Sonza Reorda,
Massimo Violante:
A New Approach to the Analysis of Single Event Transients in VLSI Circuits.
J. Electronic Testing 20(5): 511-521 (2004) |
| 45 | EE | Matteo Sonza Reorda,
Massimo Violante:
Efficient analysis of single event transients.
Journal of Systems Architecture 50(5): 239-246 (2004) |
| 2003 |
|---|
| 44 | EE | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor.
DATE 2003: 10602-10607 |
| 43 | EE | Paolo Bernardi,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories.
DATE 2003: 10720-10725 |
| 42 | EE | Abdelaziz Ammari,
Régis Leveugle,
Matteo Sonza Reorda,
Massimo Violante:
Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels.
DFT 2003: 336-343 |
| 41 | EE | J. Pérez,
Matteo Sonza Reorda,
Massimo Violante:
Dependability Analysis of CAN Networks: An Emulation-Based Approach.
DFT 2003: 537- |
| 40 | EE | O. Goloubeva,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Soft-Error Detection Using Control Flow Assertions.
DFT 2003: 581-588 |
| 39 | EE | Matteo Sonza Reorda,
Massimo Violante:
Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits.
FPL 2003: 616-626 |
| 38 | EE | Matteo Sonza Reorda,
Massimo Violante:
Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits.
IOLTS 2003: 101-105 |
| 37 | EE | Massimo Violante,
M. Ceschia,
Matteo Sonza Reorda,
Alessandro Paccagnella,
Paolo Bernardi,
Maurizio Rebaudengo,
D. Bortolato,
M. Bellato,
P. Zambolin,
A. Candelori:
Analyzing SEU Effects in SRAM-based FPGAs.
IOLTS 2003: 119-123 |
| 36 | EE | O. Goloubeva,
Matteo Sonza Reorda,
Massimo Violante:
An RT-level Concurrent Error Detection Technique for Data Dominated Systems.
IOLTS 2003: 159 |
| 35 | EE | Davide Appello,
Paolo Bernardi,
Alessandra Fudoli,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Vincenzo Tancorre,
Massimo Violante:
Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores.
ITC 2003: 379-385 |
| 34 | EE | J. Pérez,
Matteo Sonza Reorda,
Massimo Violante:
Accurate Dependability Analysis of CAN-Based Networked Systems.
SBCCI 2003: 337-342 |
| 33 | EE | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor.
J. Electronic Testing 19(5): 577-584 (2003) |
| 32 | EE | Pierluigi Civera,
Luca Macchiarulo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
New techniques for efficiently assessing reliability of SOCs.
Microelectronics Journal 34(1): 53-61 (2003) |
| 2002 |
|---|
| 31 | EE | Matteo Sonza Reorda,
Massimo Violante:
Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments.
DFT 2002: 263-274 |
| 30 | EE | Pierluigi Civera,
Luca Macchiarulo,
Massimo Violante:
A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis.
DFT 2002: 31-39 |
| 29 | EE | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
A New Functional Fault Model for FPGA Application-Oriented Testing.
DFT 2002: 372-380 |
| 28 | EE | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs.
FPL 2002: 607-615 |
| 27 | EE | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Analysis of SEU Effects in a Pipelined Processor.
IOLTW 2002: 112-116 |
| 26 | EE | Pierluigi Civera,
Luca Macchiarulo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits.
J. Electronic Testing 18(3): 261-271 (2002) |
| 2001 |
|---|
| 25 | EE | Pierluigi Civera,
Luca Macchiarulo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
FPGA-Based Fault Injection for Microprocessor Systems.
Asian Test Symposium 2001: 304- |
| 24 | EE | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero,
Massimo Violante:
On the test of microprocessor IP cores.
DATE 2001: 209-213 |
| 23 | EE | Ph. Cheynet,
B. Nicolescu,
Raoul Velazco,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
System safety through automatic high-level code transformations: an experimental evaluation.
DATE 2001: 297-301 |
| 22 | EE | Pierluigi Civera,
Luca Macchiarulo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits .
DFT 2001: 250-258 |
| 21 | EE | Pierluigi Civera,
Luca Macchiarulo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits.
FPL 2001: 493-502 |
| 20 | EE | Pierluigi Civera,
Luca Macchiarulo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Exploiting FPGA for Accelerating Fault Injection Experiments.
IOLTW 2001: 9-13 |
| 19 | EE | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante,
Marco Torchiano:
A Source-to-Source Compiler for Generating Dependable Software.
SCAM 2001: 35-44 |
| 18 | EE | Marcello Lajolo,
Matteo Sonza Reorda,
Massimo Violante:
Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs.
VLSI Design 2001: 371- |
| 2000 |
|---|
| 17 | EE | Marcello Lajolo,
Luciano Lavagno,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Automatic test bench generation for simulation-based validation.
CODES 2000: 136-140 |
| 16 | EE | Marcello Lajolo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante,
Luciano Lavagno:
Evaluating System Dependability in a Co-Design Framework.
DATE 2000: 586-590 |
| 15 | EE | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Marco Torchiano,
Massimo Violante:
An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications.
DFT 2000: 257-265 |
| 14 | | Fulvio Corno,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Prediction of Power Requirements for High-Speed Circuits.
EvoWorkshops 2000: 247-254 |
| 13 | EE | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero,
Massimo Violante:
A genetic algorithm-based system for generating test programs for microprocessor IP cores.
ICTAI 2000: 195-198 |
| 12 | EE | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante,
Ph. Cheynet,
B. Nicolescu,
Raoul Velazco:
Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures.
IOLTW 2000: 17- |
| 11 | EE | B. Parrotta,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
New Techniques for Accelerating Fault Injection in VHDL Descriptions.
IOLTW 2000: 61-66 |
| 10 | EE | Marcello Lajolo,
Luciano Lavagno,
Matteo Sonza Reorda,
Massimo Violante:
Early Power Estimation for System-on-Chip Designs.
PATMOS 2000: 108-117 |
| 9 | EE | B. Parrotta,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Speeding-Up Fault Injection Campaigns in VHDL Models.
SAFECOMP 2000: 27-36 |
| 8 | EE | Fulvio Corno,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Giovanni Squillero,
Massimo Violante:
Low Power BIST via Non-Linear Hybrid Cellular Automata.
VTS 2000: 29-34 |
| 1999 |
|---|
| 7 | EE | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Marco Torchiano,
Massimo Violante:
Soft-Error Detection through Software Fault-Tolerance Techniques.
DFT 1999: 210-218 |
| 6 | EE | Fulvio Corno,
Matteo Sonza Reorda,
Maurizio Rebaudengo,
Massimo Violante:
Optimal Vector Selection for Low Power BIST.
DFT 1999: 219-226 |
| 5 | | Fulvio Corno,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Test Pattern Generation Under Low Power Constraints.
EvoWorkshops 1999: 162-170 |
| 4 | EE | Fulvio Corno,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
ALPS: A Peak Power Estimation Tool for Sequential Circuits.
Great Lakes Symposium on VLSI 1999: 350-353 |
| 3 | EE | Fulvio Corno,
Uwe Gläser,
Paolo Prinetto,
Matteo Sonza Reorda,
Heinrich Theodor Vierhaus,
Massimo Violante:
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 191-202 (1999) |
| 1998 |
|---|
| 2 | EE | Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda,
Massimo Violante:
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection.
DATE 1998: 670- |
| 1997 |
|---|
| 1 | EE | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG.
Asian Test Symposium 1997: 68-73 |
