| 2007 |
|---|
| 5 | EE | Yu-Shen Yang,
Subarnarekha Sinha,
Andreas G. Veneris,
Robert K. Brayton:
Automating Logic Rectification by Approximate SPFDs.
ASP-DAC 2007: 402-407 |
| 2006 |
|---|
| 4 | EE | Yu-Shen Yang,
Andreas G. Veneris,
Paul J. Thadikaran,
Srikanth Venkataraman:
Extraction error modeling and automated model debugging in high-performance custom designs.
IEEE Trans. VLSI Syst. 14(7): 763-776 (2006) |
| 2005 |
|---|
| 3 | EE | Yu-Shen Yang,
Andreas G. Veneris,
Paul J. Thadikaran,
Srikanth Venkataraman:
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs.
DATE 2005: 996-1001 |
| 2003 |
|---|
| 2 | EE | Yu-Shen Yang,
Jiang Brandon Liu,
Paul J. Thadikaran,
Andreas G. Veneris:
Extraction Error Diagnosis and Correction in High-Performance Designs.
ITC 2003: 423-430 |
| 1 | EE | Yu-Shen Yang,
Jiang Brandon Liu,
Paul J. Thadikaran,
Andreas G. Veneris:
Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs.
MTV 2003: 54-59 |
