| 2009 |
|---|
| 106 | EE | Patrick Girard,
Jeremy Seligman:
An Analytic Logic of Aggregation.
ICLA 2009: 146-161 |
| 105 | EE | Youssef Benabboud,
Alberto Bosio,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Laroussi Bouzaida,
Isabelle Izaute:
A case study on logic diagnosis for System-on-Chip.
ISQED 2009: 253-259 |
| 2008 |
|---|
| 104 | EE | A. Ney,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian,
V. Gouin:
A Design-for-Diagnosis Technique for SRAM Write Drivers.
DATE 2008: 1480-1485 |
| 103 | EE | Dimitris Gizopoulos,
Kaushik Roy,
Patrick Girard,
Nicola Nicolici,
Xiaoqing Wen:
Power-Aware Testing and Test Strategies for Low Power Devices.
DATE 2008 |
| 102 | EE | Alberto Bosio,
Patrick Girard,
Serge Pravossoudovitch,
Paolo Bernardi:
SoC Symbolic Simulation: a case study on delay fault testing.
DDECS 2008: 320-325 |
| 101 | EE | Alexandre Rousset,
Alberto Bosio,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Improving Diagnosis Resolution without Physical Information.
DELTA 2008: 210-215 |
| 100 | EE | Julien Vial,
Alberto Bosio,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Using TMR Architectures for Yield Improvement.
DFT 2008: 7-15 |
| 99 | EE | Sybille Caffiau,
Patrick Girard,
Dominique L. Scapin,
Laurent Guittet,
Loé Sanou:
Assessment of Object Use for Task Modeling.
TAMODIA/HCSE 2008: 14-28 |
| 98 | EE | A. Ney,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian,
V. Gouin:
An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing.
VTS 2008: 89-94 |
| 97 | EE | Nicola Nicolici,
Patrick Girard:
Guest Editorial.
J. Electronic Testing 24(4): 325-326 (2008) |
| 96 | EE | Nabil Badereddine,
Zhanglei Wang,
Patrick Girard,
Krishnendu Chakrabarty,
Arnaud Virazel,
Serge Pravossoudovitch,
Christian Landrault:
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.
J. Electronic Testing 24(4): 353-364 (2008) |
| 2007 |
|---|
| 95 | | Patrick Girard,
Andrzej Krasniewski,
Elena Gramatová,
Adam Pawlak,
Tomasz Garbolino:
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007
IEEE Computer Society 2007 |
| 94 | EE | A. Ney,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian:
Slow write driver faults in 65nm SRAM technology: analysis and March test solution.
DATE 2007: 528-533 |
| 93 | | Alexandre Rousset,
Alberto Bosio,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
A Mixed Approach for Unified Logic Diagnosis.
DDECS 2007: 239-242 |
| 92 | EE | Alexandre Rousset,
Alberto Bosio,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
DERRIC: A Tool for Unified Logic Diagnosis.
European Test Symposium 2007: 13-20 |
| 91 | EE | O. Ginez,
Jean Michel Daga,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories.
European Test Symposium 2007: 77-84 |
| 90 | EE | A. Ney,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian:
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.
European Test Symposium 2007: 97-104 |
| 89 | EE | Sybille Caffiau,
Patrick Girard,
Dominique L. Scapin,
Laurent Guittet:
Generating Interactive Applications from Task Models: A Hard Challenge.
TAMODIA 2007: 267-272 |
| 88 | EE | A. Ney,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian:
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.
VTS 2007: 361-368 |
| 87 | EE | O. Ginez,
Jean Michel Daga,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window.
VTS 2007: 47-52 |
| 86 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian:
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits.
J. Electronic Testing 23(5): 435-444 (2007) |
| 2006 |
|---|
| 85 | EE | Luigi Dilillo,
Paul M. Rosinger,
Bashir M. Al-Hashimi,
Patrick Girard:
Minimizing test power in SRAM through reduction of pre-charge activity.
DATE 2006: 1159-1164 |
| 84 | | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian:
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.
DDECS 2006: 256-261 |
| 83 | EE | Loé Sanou,
Patrick Girard,
Laurent Guittet:
Comparaison de deux méthodes pour implémenter la programmation sur exemple.
IHM 2006: 265-268 |
| 82 | EE | Nabil Badereddine,
Patrick Girard,
Serge Pravossoudovitch,
Christian Landrault,
Arnaud Virazel,
Hans-Joachim Wunderlich:
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.
VLSI-SoC 2006: 403-408 |
| 81 | EE | O. Ginez,
Jean Michel Daga,
Marylene Combe,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
An Overview of Failure Mechanisms in Embedded Flash Memories.
VTS 2006: 108-113 |
| 80 | EE | Zahir Albadawi,
Benoit Boulet,
Robert DiRaddo,
Patrick Girard,
Alexandre Rail,
Vincent Thomson:
Agent-based control of manufacturing processes.
IJMR 1(4): 466-481 (2006) |
| 79 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
A Gated Clock Scheme for Low Power Testing of Logic Cores.
J. Electronic Testing 22(1): 89-99 (2006) |
| 78 | EE | Patrick Girard,
Olivier Héron,
Serge Pravossoudovitch,
Michel Renovell:
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.
J. Electronic Testing 22(2): 161-172 (2006) |
| 77 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Simone Borri,
Magali Bastian Hage-Hassan:
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions.
J. Electronic Testing 22(3): 287-296 (2006) |
| 76 | EE | Luigi Dilillo,
Paul M. Rosinger,
Bashir M. Al-Hashimi,
Patrick Girard:
Reducing Power Dissipation in SRAM during Test.
J. Low Power Electronics 2(2): 271-280 (2006) |
| 2005 |
|---|
| 75 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian:
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.
DAC 2005: 857-862 |
| 74 | EE | Nicolas Guibert,
Laurent Guittet,
Patrick Girard:
Validation d'une approche " basée sur exemples " pour l'apprentissage de la programmation.
IHM 2005: 147-154 |
| 73 | EE | Nabil Badereddine,
Patrick Girard,
Arnaud Virazel,
Serge Pravossoudovitch,
Christian Landrault:
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives.
PATMOS 2005: 540-549 |
| 72 | EE | Nabil Badereddine,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Christian Landrault:
Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.
VLSI-SoC 2005: 267-281 |
| 71 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian Hage-Hassan:
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures.
VTS 2005: 183-188 |
| 70 | EE | Patrick Girard,
Olivier Héron,
Serge Pravossoudovitch,
Michel Renovell:
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs.
J. Electronic Testing 21(1): 43-55 (2005) |
| 69 | EE | Simone Borri,
Magali Bastian Hage-Hassan,
Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel:
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.
J. Electronic Testing 21(2): 169-179 (2005) |
| 68 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Simone Borri,
Magali Bastian Hage-Hassan:
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.
J. Electronic Testing 21(5): 551-561 (2005) |
| 67 | EE | Patrick Girard:
Welcome to the Journal of Low Power Electronics.
J. Low Power Electronics 1(1): 1-2 (2005) |
| 66 | EE | Patrick Girard,
Yannick Bonhomme:
Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing.
J. Low Power Electronics 1(1): 85-95 (2005) |
| 2004 |
|---|
| 65 | EE | Nicolas Guibert,
Patrick Girard,
Laurent Guittet:
Example-based programming: a pertinent visual approach for learning to program.
AVI 2004: 358-361 |
| 64 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Simone Borri,
Magali Bastian Hage-Hassan:
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.
Asian Test Symposium 2004: 266-271 |
| 63 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains.
DATE 2004: 62-67 |
| 62 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains.
DELTA 2004: 287-294 |
| 61 | EE | Patrick Girard,
Olivier Héron,
Serge Pravossoudovitch,
Michel Renovell:
High Quality TPG for Delay Faults in Look-Up Tables of FPGAs.
DELTA 2004: 83-88 |
| 60 | | Yamine Aït Ameur,
Benoit Breholée,
Patrick Girard,
Laurent Guittet,
Francis Jambon:
Formal Verification and Validation of Interactive Systems Specifications.
Human Error, Safety and Systems Development 2004: 61-76 |
| 59 | EE | Patrick Girard,
Olivier Héron,
Serge Pravossoudovitch,
Michel Renovell:
BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs.
IOLTS 2004: 187-192 |
| 58 | EE | Mickaël Baron,
Patrick Girard:
SUIDT: safe user interface design tool.
IUI 2004: 350-351 |
| 57 | EE | Benoit Boulet,
Robert DiRaddo,
Patrick Girard,
Vincent Thomson:
An agent based architecture for model based control.
SMC (2) 2004: 2002-2007 |
| 56 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Simone Borri:
March iC-: An Improved Version of March C- for ADOFs Detection.
VTS 2004: 129-138 |
| 55 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
Power-Driven Routing-Constrained Scan Chain Design.
J. Electronic Testing 20(6): 647-660 (2004) |
| 2003 |
|---|
| 54 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Simone Borri:
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders.
Asian Test Symposium 2003: 250-255 |
| 53 | EE | Mickaël Baron,
Patrick Girard:
SUIDT: a user interface builder for secure user interfaces.
IHM 2003: 198-201 |
| 52 | EE | Nicolas Guibert,
Patrick Girard:
Programming by example and computer-aided teaching of algorithmics: the MELBA project.
IHM 2003: 248-251 |
| 51 | EE | Patrick Girard,
Olivier Héron,
Serge Pravossoudovitch,
Michel Renovell:
Defect Analysis for Delay-Fault BIST in FPGAs.
IOLTS 2003: 124-128 |
| 50 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.
ITC 2003: 488-493 |
| 49 | | Yamine Aït Ameur,
Mickaël Baron,
Patrick Girard:
Formal Validation of HCI User Tasks.
Software Engineering Research and Practice 2003: 732-738 |
| 48 | EE | Christophe Fagot,
Olivier Gascuel,
Patrick Girard,
Christian Landrault:
A Ring Architecture Strategy for BIST Test Pattern Generation.
J. Electronic Testing 19(3): 223-231 (2003) |
| 2002 |
|---|
| 47 | | Patrick Girard,
Thomas Baudel,
Michel Beaudouin-Lafon,
Eric Lecolinet,
Dominique L. Scapin:
Proceedings of the 14th French-speaking conference on Human-computer interactio n, Conference Francophone sur l'Interaction Homme-Machine, IHM 2002, Poitiers, France, November 26-29, 2002
ACM 2002 |
| 46 | EE | Yannick Bonhomme,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch:
Test Power: a Big Issue in Large SOC Designs.
DELTA 2002: 447-449 |
| 45 | EE | Yannick Bonhomme,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch:
Power Driven Chaining of Flip-Flops in Scan Architectures.
ITC 2002: 796-803 |
| 44 | | Mickaël Baron,
Patrick Girard:
SUIDT: A task model based GUI-Builder.
TAMODIA 2002: 64-71 |
| 43 | EE | René David,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
On Using Efficient Test Sequences for BIST.
VTS 2002: 145-152 |
| 42 | EE | Patrick Girard:
Survey of Low-Power Testing of VLSI Circuits.
IEEE Design & Test of Computers 19(3): 82-92 (2002) |
| 41 | EE | Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel,
Hans-Joachim Wunderlich:
High Defect Coverage with Low-Power Test Sequences in a BIST Environment.
IEEE Design & Test of Computers 19(5): 44-52 (2002) |
| 40 | EE | René David,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Hardware Generation of Random Single Input Change Test Sequences.
J. Electronic Testing 18(2): 145-157 (2002) |
| 2001 |
|---|
| 39 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.
Asian Test Symposium 2001: 253-258 |
| 38 | EE | Francis Jambon,
Patrick Girard,
Yamine Aït Ameur:
Interactive System Safety and Usability Enforced with the Development Process.
EHCI 2001: 39-56 |
| 37 | EE | Mickaël Baron,
Patrick Girard:
Bringing Robustness to End-User Programming.
HCC 2001: 142- |
| 36 | EE | Guillaume Patry,
Patrick Girard:
End-User Programming in a Structured Dialogue Environment: the GIPSE Project.
HCC 2001: 212- |
| 35 | | Guillaume Texier,
Laurent Guittet,
Patrick Girard:
The dialog tool set: a new way to create the dialog component.
HCI 2001: 200-204 |
| 34 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan-Based BIST.
IOLTW 2001: 87-89 |
| 33 | | René David,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Random Adjacent Sequences: An Efficient Solution for Logic BIST.
VLSI-SOC 2001: 413-424 |
| 32 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Hans-Joachim Wunderlich:
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.
VTS 2001: 306-311 |
| 31 | EE | Arnaud Virazel,
René David,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch:
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences.
J. Electronic Testing 17(3-4): 233-241 (2001) |
| 2000 |
|---|
| 30 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
An adjacency-based test pattern generator for low power BIST design.
Asian Test Symposium 2000: 459-464 |
| 29 | EE | Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults.
IOLTW 2000: 121-126 |
| 28 | EE | Patrick Girard:
Low Power Testing of VLSI Circuits: Problems and Solutions.
ISQED 2000: 173-180 |
| 27 | | Patrick Girard,
Christian Landrault,
Loïs Guiller,
Serge Pravossoudovitch:
Low power BIST design by hypergraph partitioning: methodology and architectures.
ITC 2000: 652-661 |
| 26 | EE | Laurent Bréhélin,
Olivier Gascuel,
Gilles Caraux,
Patrick Girard,
Christian Landrault:
Hidden Markov and Independence Models with Patterns for Sequential BIST.
VTS 2000: 359-368 |
| 25 | EE | Salvador Manich,
A. Gabarró,
M. Lopez,
Joan Figueras,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
P. Teixeira,
M. Santos:
Low Power BIST by Filtering Non-Detecting Vectors.
J. Electronic Testing 16(3): 193-202 (2000) |
| 1999 |
|---|
| 24 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.
Asian Test Symposium 1999: 89-94 |
| 23 | | Guillaume Patry,
Patrick Girard:
GIPSE, A Model-Based System for CAD Software.
CADUI 1999: 61-72 |
| 22 | | Francis Jambon,
Patrick Girard,
Yohann Boisdron:
Dialogue Validation from Task Analysis.
DSV-IS 1999: 205-224 |
| 21 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.
Great Lakes Symposium on VLSI 1999: 24- |
| 20 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Joan Figueras,
Salvador Manich,
P. Teixeira,
M. Santos:
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.
ISCAS (1) 1999: 110-113 |
| 19 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
A Test Vector Inhibiting Technique for Low Energy BIST Design.
VTS 1999: 407-412 |
| 18 | EE | Patrick Girard,
Christian Landrault,
V. Moreda,
Serge Pravossoudovitch,
Arnaud Virazel:
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits.
J. Electronic Testing 14(1-2): 95-102 (1999) |
| 1998 |
|---|
| 17 | EE | Christophe Fagot,
Olivier Gascuel,
Patrick Girard,
Christian Landrault:
A Ring Architecture Strategy for BIST Test Pattern Generation.
Asian Test Symposium 1998: 418-423 |
| 16 | EE | Patrick Girard,
Christian Landrault,
V. Moreda,
Serge Pravossoudovitch,
Arnaud Virazel:
A BIST Structure to Test Delay Faults in a Scan Environment.
Asian Test Symposium 1998: 435-439 |
| 15 | | Yamine Aït Ameur,
Patrick Girard,
Francis Jambon:
A Uniform Approach for Specification and Design of Interactive Systems: the B Method.
DSV-IS (2) 1998: 51-67 |
| 14 | | Yamine Aït Ameur,
Patrick Girard,
Francis Jambon:
Using the B Formal Approach for Incremental Specification Design of Interactiv Systems.
EHCI 1998: 91-109 |
| 1997 |
|---|
| 13 | EE | Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
D. Severac:
A gate resizing technique for high reduction in power consumption.
ISLPED 1997: 281-286 |
| 12 | | Christophe Fagot,
Patrick Girard,
Christian Landrault:
On Using Machine Learning for Logic BIST.
ITC 1997: 338-346 |
| 11 | EE | Patrick Girard,
Christian Landrault,
V. Moreda,
Serge Pravossoudovitch:
An optimized BIST test pattern generator for delay testing.
VTS 1997: 94-100 |
| 10 | EE | Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
D. Severac:
A non-iterative gate resizing algorithm for high reduction in power consumption.
Integration 24(1): 37-52 (1997) |
| 1996 |
|---|
| 9 | | Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
B. Rodriguez:
A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms.
ITC 1996: 286-293 |
| 8 | EE | S. Cremoux,
Christophe Fagot,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch:
A new test pattern generation method for delay fault testing.
VTS 1996: 296-301 |
| 1995 |
|---|
| 7 | | Yamine Aït Ameur,
Frederic Besnard,
Patrick Girard,
Guy Pierra,
Jean-Claude Potier:
Formal Specification and Metaprogramming in the EXPRESS Language.
SEKE 1995: 181-188 |
| 6 | EE | Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
B. Rodriguez:
Diagnostic of path and gate delay faults in non-scan sequential circuits.
VTS 1995: 380-386 |
| 5 | EE | Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch:
An advanced diagnostic method for delay faults in combinational faulty circuits.
J. Electronic Testing 6(3): 277-294 (1995) |
| 1994 |
|---|
| 4 | | D. Dumas,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch:
Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis.
EDAC-ETC-EUROASIC 1994: 518-523 |
| 1993 |
|---|
| 3 | | D. Dumas,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch:
An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation.
ITC 1993: 705-713 |
| 1992 |
|---|
| 2 | EE | Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch:
A Novel Approach to Delay-Fault Diagnosis.
DAC 1992: 357-360 |
| 1 | EE | Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch:
Delay-Fault Diagnosis by Critical-Path Tracing.
IEEE Design & Test of Computers 9(4): 27-32 (1992) |
