| 2007 |
|---|
| 6 | EE | Matthias Beck,
Olivier Barondeau,
Martin Kaibel,
Frank Poehl,
Xijiang Lin,
Ron Press:
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality
CoRR abs/0710.4763: (2007) |
| 2006 |
|---|
| 5 | EE | Frank Poehl,
Jan Rzeha,
Matthias Beck,
Michael Gössel,
Ralf Arnold,
Peter Ossimitz:
On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture.
European Test Symposium 2006: 239-246 |
| 2005 |
|---|
| 4 | EE | Matthias Beck,
Olivier Barondeau,
Martin Kaibel,
Frank Poehl,
Xijiang Lin,
Ron Press:
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality.
DATE 2005: 56-61 |
| 3 | EE | Matthias Beck,
Olivier Barondeau,
Frank Poehl,
Xijiang Lin,
Ron Press:
Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study.
VTS 2005: 223-228 |
| 2003 |
|---|
| 2 | EE | Frank Poehl,
Matthias Beck,
Ralf Arnold,
Peter Muhmenthaler,
Nagesh Tamarapalli,
Mark Kassab,
Nilanjan Mukherjee,
Janusz Rajski:
Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions.
ITC 2003: 1211-1220 |
| 1999 |
|---|
| 1 | EE | Frank Poehl,
Walter Anheier:
Quality Determination for Gate Delay Fault Tests Considering Three-State Elements.
J. Electronic Testing 14(1-2): 49-55 (1999) |
