Peter Wohl

2007
23	EE	Peter Wohl, John A. Waicukauski, Sanjay Patel: Automated Design and Insertion of Optimal One-Hot Bus Encoders. VTS 2007: 409-415
22	EE	Peter Wohl, John A. Waicukauski, Rohit Kapur, S. Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini: Minimizing the Impact of Scan Compression. VTS 2007: 67-74
2005
21	EE	Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew: Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST. VTS 2005: 359-365
2004
20	EE	Peter Wohl, John A. Waicukauski, Sanjay Patel: Scalable selector architecture for x-tolerant deterministic BIST. DAC 2004: 934-939
2003
19	EE	Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin: Efficient compression and application of deterministic patterns in a logic BIST architecture. DAC 2003: 566-569
18	EE	Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin: X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture. ITC 2003: 727-736
17	EE	Peter Wohl, Leendert M. Huisman: Analysis and Design of Optimal Combinational Compactors. VTS 2003: 101-106
2002
16	EE	Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston: Effective diagnostics through interval unloads in a BIST environment. DAC 2002: 249-254
2001
15		Peter Wohl, John A. Waicukauski, Thomas W. Williams: Design of compactors for signature-analyzers in built-in self-test. ITC 2001: 54-63
2000
14		Peter Wohl, John A. Waicukauski: Optimizing the flattened test-generation model for very large designs. ITC 2000: 681-690
13	EE	Peter Wohl, Nathan Biggs: P1450.1: STIL for the Simulation Environmen. VTS 2000: 389-394
1999
12		Peter Wohl, John A. Waicukauski: Using Verilog simulation libraries for ATPG. ITC 1999: 1011-1020
11		Peter Wohl: Output in still, input in still. ITC 1999: 1148
1998
10	EE	Peter Wohl, John A. Waicukauski: Extracting gate-level networks from simulation tables. ITC 1998: 622-631
9	EE	Peter Wohl, John A. Waicukauski: Defining ATPG rules checking in STIL. ITC 1998: 971-979
1997
8		Peter Wohl, John A. Waicukauski: A Unified Interface for Scan Test Generation Based on STIL. ITC 1997: 1011-1019
7	EE	Peter Wohl, John A. Waicukauski: Using ATPG for clock rules checking in complex scan design. VTS 1997: 130-136
1996
6		Peter Wohl, John A. Waicukauski: Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates. ITC 1996: 13-20
5	EE	Peter Wohl, John A. Waicukauski, Matthew Graf: Testing "untestable" faults in three-state circuits. VTS 1996: 324-331
1992
4		Peter Wohl, Thomas W. Christopher: Designing Conceptual Clustering for Parallel Implementation. ICPP (3) 1992: 318-325
1991
3		Peter Wohl, Thomas W. Christopher: Parallel Conceptual Clustering through Message-Driven Computing. ICPP (2) 1991: 286-287
2		Peter Wohl, Thomas W. Christopher: A Parallel Processing Approach to Incremental Conceptual Clustering. IPPS 1991: 240-245
1990
1		Peter Wohl, Thomas W. Christopher: SIMD Neural Net Mapping on MIMD Architectures. ICPP (1) 1990: 587-588

Coauthor Index

1	Minesh B. Amin	[18] [19]
2	Nathan Biggs	[13]
3	Thomas W. Christopher	[1] [2] [3] [4]
4	Emil Gizdarski	[21] [22]
5	Matthew Graf	[5]
6	Cy Hay	[21]
7	Leendert M. Huisman	[17]
8	P. Jaini	[22]
9	Rohit Kapur	[22]
10	Gregory A. Maston	[16]
11	Ben Mathew	[21]
12	Sanjay Patel	[16] [18] [19] [20] [21] [23]
13	S. Ramnath	[22]
14	John A. Waicukauski	[5] [6] [7] [8] [9] [10] [12] [14] [15] [16] [18] [19] [20] [21] [22] [23]
15	Thomas W. Williams	[15] [22]

Colors in the list of coauthors