| 2007 |
|---|
| 10 | EE | Laurent Lopez,
Jean Michel Portal,
Didier Née:
A New Embedded Measurement Structure for eDRAM Capacitor
CoRR abs/0710.4736: (2007) |
| 2005 |
|---|
| 9 | EE | Laurent Lopez,
Jean Michel Portal,
Didier Née:
A New Embedded Measurement Structure for eDRAM Capacitor.
DATE 2005: 462-463 |
| 8 | EE | B. Saillet,
Jean Michel Portal,
Didier Née:
Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring.
DFT 2005: 131-139 |
| 7 | EE | Jean Michel Portal,
H. Aziza,
Didier Née:
EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement.
J. Electronic Testing 21(1): 33-42 (2005) |
| 2003 |
|---|
| 6 | EE | L. Forli,
Jean Michel Portal,
Didier Née,
Bertrand Borot:
Infrastructure IP for Back-End Yield Improvement.
ITC 2003: 1129-1134 |
| 5 | EE | Jean Michel Portal,
H. Aziza,
Didier Née:
EEPROM Memory: Threshold Voltage Built In Self Diagnosis.
ITC 2003: 23-28 |
| 2002 |
|---|
| 4 | EE | Jean Michel Portal,
L. Forli,
Didier Née:
Floating-gate EEPROM cell: threshold voltage sensibility to geometry.
ISCAS (1) 2002: 557-560 |
| 3 | EE | Jean Michel Portal,
L. Forli,
Didier Née:
Floating-gate EEPROM cell model based on MOS model 9.
ISCAS (3) 2002: 799-802 |
| 2 | EE | Jean Michel Portal,
L. Forli,
H. Aziza,
Didier Née:
An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell.
ITC 2002: 31-36 |
| 1 | EE | Jean Michel Portal,
L. Forli,
H. Aziza,
Didier Née:
An Automated Design Methodology for EEPROM Cell (ADE).
MTDT 2002: 137-142 |
