Sudipta Bhawmik

2003
20	EE	Michael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson, Peter Harrod: The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data. ITC 2003: 998-1007
2002
19	EE	Subhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik: Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch. VLSI Design 2002: 598-603
18	EE	Subhayu Basu, Indranil Sengupta, Dipanwita Roy Chowdhury, Sudipta Bhawmik: An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch. J. Electronic Testing 18(4-5): 475-485 (2002)
2001
17		Sudipta Bhawmik: ntroduction to SystemC. VLSI Design 2001: 7-8
2000
16		Frank P. Higgins, Sudipta Bhawmik: Core Based ASIC Design. VLSI Design 2000: 10
15	EE	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik: A BIST scheme for RTL circuits based on symbolic testabilityanalysis. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 111-128 (2000)
14	EE	Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik: On improving test quality of scan-based BIST. IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 928-938 (2000)
1999
13	EE	Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik: Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme. DAC 1999: 748-753
12		Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik: POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing. VLSI Design 1999: 416-422
1998
11	EE	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik: A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. DAC 1998: 554-559
10	EE	Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng: An almost full-scan BIST solution-higher fault coverage and shorter test application time. ITC 1998: 1065-
9	EE	Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik: A BIST scheme for the detection of path-delay faults. ITC 1998: 422-
8	EE	Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik: Efficient test-point selection for scan-based BIST. IEEE Trans. VLSI Syst. 6(4): 667-676 (1998)
1997
7	EE	Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik: A Hybrid Algorithm for Test Point Selection for Scan-Based BIST. DAC 1997: 478-483
6	EE	Sudipta Bhawmik, Indradeep Ghosh: A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits. VLSI Design 1997: 284-288
1995
5	EE	Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik: Integration of partial scan and built-in self-test. J. Electronic Testing 7(1-2): 125-137 (1995)
1993
4		Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik: PSBIST: A Partial-Scan Based Built-In Self-Test Scheme. ITC 1993: 507-516
1991
3	EE	Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin: Enhanced Controllability for IDDQ Test Sets Using Partial Scan. DAC 1991: 278-281
1989
2		Prasad R. Chalasani, Sudipta Bhawmik, Anurag Acharya, P. Palchaudhuri: Design of Testable VLSI Circuits with Minumum Area Overhead. IEEE Trans. Computers 38(10): 1460-1462 (1989)
1988
1	EE	Sudipta Bhawmik, P. Pal Chaudhuri: DFTEXPERT: An Expert System for Design of Testable VLSI Circuits. IEA/AIE (Vol. 1) 1988: 388-396

Coauthor Index

1	Anurag Acharya	[2]
2	Subhayu Basu	[18] [19]
3	Robert Bencivenga	[3]
4	Tapan J. Chakraborty	[3] [9]
5	Prasad R. Chalasani	[2]
6	P. Pal Chaudhuri	[1]
7	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[7] [8] [10] [13] [14]
8	Dipanwita Roy Chowdhury	[18] [19]
9	Scott Davidson	[20]
10	Indradeep Ghosh	[6] [11] [15]
11	Pradipta Ghosh	[20]
12	Peter Harrod	[20]
13	Frank P. Higgins	[16]
14	Niraj K. Jha	[11] [15]
15	Chih-Jen Lin	[3] [4] [5] [7] [8]
16	Nilanjan Mukherjee	[9]
17	Debdeep Mukhopadhyay	[19]
18	P. Palchaudhuri	[2]
19	Kaushik Roy	[12]
20	Indranil Sengupta	[18] [19]
21	Huan-Chih Tsai	[7] [8] [10] [13] [14]
22	Michael G. Wahl	[20]
23	Kamran Zarrineh	[20]
24	Xiaodong Zhang	[12]
25	Yervant Zorian	[4] [5]

Colors in the list of coauthors