| 2008 |
|---|
| 65 | EE | Hooman Farkhani,
Mohammad Maymandi-Nejad,
Manoj Sachdev:
A fully digital ADC using a new delay element with enhanced linearity.
ISCAS 2008: 2406-2409 |
| 64 | EE | Shah M. Jahinuzzaman,
Mohammad Sharifkhani,
Manoj Sachdev:
Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model.
ISQED 2008: 207-212 |
| 2007 |
|---|
| 63 | EE | David Rennie,
Manoj Sachdev:
A Novel Tri-State Binary Phase Detector.
ISCAS 2007: 185-188 |
| 62 | EE | David Rennie,
Manoj Sachdev:
Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits.
ISQED 2007: 305-310 |
| 61 | EE | Mohammad Sharifkhani,
Manoj Sachdev:
Segmented Virtual Ground Architecture for Low-Power Embedded SRAM.
IEEE Trans. VLSI Syst. 15(2): 196-205 (2007) |
| 60 | EE | Mohamed Elgebaly,
Manoj Sachdev:
Variation-Aware Adaptive Voltage Scaling System.
IEEE Trans. VLSI Syst. 15(5): 560-571 (2007) |
| 2006 |
|---|
| 59 | EE | Mohammad Sharifkhani,
Manoj Sachdev:
A phase-domain 2nd-order continuous time Delta-Sigma-modulator for frequency digitization.
ISCAS 2006 |
| 58 | EE | Mohammad Sharifkhani,
Manoj Sachdev:
A low power SRAM architecture based on segmented virtual grounding.
ISLPED 2006: 256-261 |
| 57 | EE | Mohammad Sharifkhani,
Shah M. Jahinuzzaman,
Manoj Sachdev:
Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests.
MTDT 2006: 55-64 |
| 56 | EE | Mohammad Maymandi-Nejad,
Manoj Sachdev:
DTMOS Technique for Low-Voltage Analog Circuits.
IEEE Trans. VLSI Syst. 14(10): 1151-1156 (2006) |
| 55 | EE | Nitin Mohan,
W. Fung,
Derek Wright,
Manoj Sachdev:
Design techniques and test methodology for low-power TCAMs.
IEEE Trans. VLSI Syst. 14(6): 573-586 (2006) |
| 54 | EE | Bashir M. Al-Hashimi,
Dimitris Gizopoulos,
Manoj Sachdev,
Adit D. Singh:
New JETTA Editors, 2006.
J. Electronic Testing 22(1): 9-10 (2006) |
| 53 | EE | Oleg Semenov,
H. Sarbishaei,
Valery Axelrad,
Manoj Sachdev:
Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices.
Microelectronics Journal 37(6): 526-533 (2006) |
| 2005 |
|---|
| 52 | EE | Mohammad Maymandi-Nejad,
Manoj Sachdev:
A 0.8V Delta-Sigma modulator using DTMOS technique.
ISCAS (4) 2005: 3684-3687 |
| 51 | EE | Oleg Semenov,
H. Sarbishaei,
Manoj Sachdev:
Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment.
ISQED 2005: 427-432 |
| 50 | EE | Bhaskar Chatterjee,
Manoj Sachdev:
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology.
IEEE Trans. VLSI Syst. 13(11): 1296-1304 (2005) |
| 49 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ram Krishnamurthy:
Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies.
Microelectronics Journal 36(9): 801-809 (2005) |
| 2004 |
|---|
| 48 | EE | Arman Vassighi,
Ali Keshavarzi,
Siva Narendra,
Gerhard Schrom,
Yibin Ye,
Seri Lee,
Greg Chrysler,
Manoj Sachdev,
Vivek De:
Design optimizations for microprocessors at low temperature.
DAC 2004: 2-5 |
| 47 | | Nitin Mohan,
Manoj Sachdev:
Low power dual matchline ternary content addressable memory.
ISCAS (2) 2004: 633-636 |
| 46 | | Christine Kwong,
Bhaskar Chatterjee,
Manoj Sachdev:
Modeling and designing energy-delay optimized wide domino circuits.
ISCAS (2) 2004: 921-924 |
| 45 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ram Krishnamurthy:
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies.
ISLPED 2004: 248-251 |
| 44 | EE | Mohamed Elgebaly,
Manoj Sachdev:
Efficient adaptive voltage scaling system through on-chip critical path emulation.
ISLPED 2004: 375-380 |
| 43 | EE | Shahab Ardalan,
Manoj Sachdev:
An Overview of Substrate Noise Reduction Techniques.
ISQED 2004: 291-296 |
| 42 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ram Krishnamurthy:
Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies.
ISQED 2004: 415-420 |
| 41 | EE | Andrei Pavlov,
Manoj Sachdev,
José Pineda de Gyvez:
AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold.
ITC 2004: 1006-1015 |
| 40 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ali Keshavarzi:
A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs.
ITC 2004: 1108-1117 |
| 39 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ali Keshavarzi:
DFT for Delay Fault Testing of High-Performance Digital Circuits.
IEEE Design & Test of Computers 21(3): 248-258 (2004) |
| 38 | EE | Mohammad Maymandi-Nejad,
Manoj Sachdev:
Correction to "A Digitally Programmable Delay Element: Design and Analysis".
IEEE Trans. VLSI Syst. 12(10): 1126-1126 (2004) |
| 37 | | Farhad H. A. Asgari,
Manoj Sachdev:
A low-power reduced swing global clocking methodology.
IEEE Trans. VLSI Syst. 12(5): 538-545 (2004) |
| 2003 |
|---|
| 36 | EE | Muhammad Nummer,
Manoj Sachdev:
DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers.
DATE 2003: 10212-10217 |
| 35 | EE | Arman Vassighi,
Oleg Semenov,
Manoj Sachdev,
Ali Keshavarzi:
Thermal Management of High Performance Microprocessors.
DFT 2003: 313-319 |
| 34 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Steven Hsu,
Ram Krishnamurthy,
Shekhar Borkar:
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies.
ISLPED 2003: 122-127 |
| 33 | EE | Derek Wright,
Manoj Sachdev:
Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie.
ITC 2003: 39-47 |
| 32 | EE | Oleg Semenov,
Arman Vassighi,
Manoj Sachdev,
Ali Keshavarzi,
Charles F. Hawkins:
Burn-in Temperature Projections for Deep Sub-micron Technologies.
ITC 2003: 95-104 |
| 31 | EE | Muhammad Nummer,
Manoj Sachdev:
Testing high-performance pipelined circuits with slow-speed testers.
ACM Trans. Design Autom. Electr. Syst. 8(4): 506-521 (2003) |
| 30 | EE | Mohammad Maymandi-Nejad,
Manoj Sachdev:
A digitally programmable delay element: design and analysis.
IEEE Trans. VLSI Syst. 11(5): 871-878 (2003) |
| 29 | EE | Muhammad Nummer,
Manoj Sachdev:
A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers.
J. Electronic Testing 19(3): 299-314 (2003) |
| 28 | EE | Oleg Semenov,
Arman Vassighi,
Manoj Sachdev:
Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing.
J. Electronic Testing 19(3): 341-352 (2003) |
| 2002 |
|---|
| 27 | EE | Arman Vassighi,
Oleg Semenov,
Manoj Sachdev,
Ali Keshavarzi:
Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI.
DFT 2002: 12-19 |
| 26 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ali Keshavarzi:
A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits.
ITC 2002: 1130-1139 |
| 25 | EE | Manoj Sachdev:
Multi-GHz Interface Devices Should Be Tested Using External Test Resources.
ITC 2002: 1231 |
| 24 | EE | Stefan Rusu,
Manoj Sachdev,
Christer Svensson,
B. Nauta:
Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract).
VLSI Design 2002: 16-17 |
| 23 | EE | Ali Keshavarzi,
James Tschanz,
Siva Narendra,
Vivek De,
W. Robert Daasch,
Kaushik Roy,
Manoj Sachdev,
Charles F. Hawkins:
Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits.
IEEE Design & Test of Computers 19(5): 36-43 (2002) |
| 2001 |
|---|
| 22 | EE | James Tschanz,
Siva Narendra,
Zhanping Chen,
Shekhar Borkar,
Manoj Sachdev,
Vivek De:
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.
ISLPED 2001: 147-152 |
| 21 | EE | Muhammad Nummer,
Manoj Sachdev:
A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency.
VTS 2001: 68-74 |
| 20 | EE | Manoj Sachdev:
Current-Based Testing for Deep-Submicron VLSIs.
IEEE Design & Test of Computers 18(2): 76-84 (2001) |
| 19 | EE | Hans G. Kerkhoff,
Han Speek,
M. Shashani,
Manoj Sachdev:
Design for Delay Testability in High-Speed Digital ICs.
J. Electronic Testing 17(3-4): 225-231 (2001) |
| 2000 |
|---|
| 18 | | Ali Keshavarzi,
Kaushik Roy,
Charles F. Hawkins,
Manoj Sachdev,
K. Soumyanath,
Vivek De:
Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ.
ITC 2000: 1051-1059 |
| 17 | EE | Hans G. Kerkhoff,
Mansour Shashaani,
Manoj Sachdev:
A Low-Speed BIST Framework for High-Performance Circuit Testing.
VTS 2000: 349-358 |
| 1999 |
|---|
| 16 | | Mansour Shashaani,
Manoj Sachdev:
A DFT technique for high performance circuit testing.
ITC 1999: 276-285 |
| 15 | EE | Manoj Sachdev,
Hans G. Kerkhoff:
Configurations for IDDQ-Testable PLAs.
IEEE Design & Test of Computers 16(2): 58-65 (1999) |
| 14 | EE | Richard Rosing,
Hans G. Kerkhoff,
Ronald J. W. T. Tangelder,
Manoj Sachdev:
Off-Chip Diagnosis of Aperture Jitter in Full-Flash Analog-to-Digital Converters.
J. Electronic Testing 14(1-2): 67-74 (1999) |
| 1998 |
|---|
| 13 | EE | Manoj Sachdev,
Peter Janssen,
Victor Zieren:
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs.
ITC 1998: 204 |
| 1997 |
|---|
| 12 | EE | Manoj Sachdev:
Open Defects in CMOS RAM Address Decoders.
IEEE Design & Test of Computers 14(2): 26-33 (1997) |
| 1996 |
|---|
| 11 | EE | Rafael Llopis,
Manoj Sachdev:
Low power, testable dual edge triggered flip-flops.
ISLPED 1996: 341-345 |
| 10 | | Manoj Sachdev:
Deep Sub-micron IDDQ Test Options.
ITC 1996: 942 |
| 9 | EE | Manoj Sachdev:
SeparateIDDQ testing of signal and bias paths in CMOS ICs for defect diagnosis.
J. Electronic Testing 8(2): 203-214 (1996) |
| 1995 |
|---|
| 8 | | Manoj Sachdev:
IDDQ and Voltage Testable CMOS Flip-flop Configurations.
ITC 1995: 534-543 |
| 7 | | Manoj Sachdev,
Bert Atzema:
Industrial Relevance of Analog IFA: A Fact or a Fiction.
ITC 1995: 61-70 |
| 6 | EE | Manoj Sachdev:
Testing Defects in Scan Chains.
IEEE Design & Test of Computers 12(4): 45-51 (1995) |
| 5 | EE | Manoj Sachdev:
Reducing the CMOS RAM test complexity withIDDQ and voltage testing.
J. Electronic Testing 6(2): 191-202 (1995) |
| 4 | EE | Manoj Sachdev:
A realistic defect oriented testability methodology for analog circuits.
J. Electronic Testing 6(3): 265-276 (1995) |
| 1994 |
|---|
| 3 | | Manoj Sachdev:
Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing.
EDAC-ETC-EUROASIC 1994: 361-365 |
| 1993 |
|---|
| 2 | | Manoj Sachdev:
Catastrophic Defects Oriented Testability Analysis of a Class AB Amplifier.
DFT 1993: 319-326 |
| 1 | | Manoj Sachdev,
Math Verstraelen:
Development of Fault Model and Test Algorithms for Embedded DRAMs.
ITC 1993: 815-824 |
