D. M. H. Walker

Duncan M. Hank Walker

2008
58	EE	Zheng Wang, D. M. H. Walker: Dynamic Compaction for High Quality Delay Test. VTS 2008: 243-248
57	EE	Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker: A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integration 41(3): 399-412 (2008)
2007
56	EE	Jing Wang, Duncan M. Hank Walker, Xiang Lu, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul J. A. M. van de Wiel, Stefan Eichenberger: Modeling Power Supply Noise in Delay Testing. IEEE Design & Test of Computers 24(3): 226-234 (2007)
2006
55	EE	Hyun Sung Kim, D. M. H. Walker: Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in {VLSI} Circuits. MTV 2006: 76-82
54	EE	Sagar S. Sabade, D. M. H. Walker: Estimation of fault-free leakage current using wafer-level spatial information. IEEE Trans. VLSI Syst. 14(1): 91-94 (2006)
2005
53	EE	Lei Wu, D. M. H. Walker: A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits. DFT 2005: 178-186
52	EE	Bin Xue, D. M. H. Walker: Is IDDQ Test of Microprocessors Feasible? MTV 2005: 63-69
51	EE	Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker: Static Compaction of Delay Tests Considering Power Supply Noise. VTS 2005: 235-240
50	EE	Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi: Longest-path selection for delay test under process variation. IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1924-1929 (2005)
2004
49	EE	Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi: Longest path selection for delay test under process variation. ASP-DAC 2004: 98-103
48	EE	Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi: PARADE: PARAmetric Delay Evaluation under Process Variation. ISQED 2004: 276-280
47	EE	Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran: K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. ITC 2004: 223-231
46	EE	Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi: A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. MTV 2004: 97-102
45	EE	Sagar S. Sabade, D. M. H. Walker: Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests. VLSI Design 2004: 889-894
44	EE	Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi: A Statistical Fault Coverage Metric for Realistic Path Delay Faults. VTS 2004: 37-42
43	EE	Sagar S. Sabade, D. M. H. Walker: On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set. VTS 2004: 65-72
42	EE	Sagar S. Sabade, D. M. H. Walker: IDDX-based test methods: A survey. ACM Trans. Design Autom. Electr. Syst. 9(2): 159-198 (2004)
41	EE	Sagar S. Sabade, D. M. H. Walker: IDDQ data analysis using neighbor current ratios. Journal of Systems Architecture 50(5): 287-294 (2004)
2003
40	EE	Sagar S. Sabade, D. M. H. Walker: CROWNE: Current Ratio Outliers with Neighbor Estimator. DFT 2003: 132-139
39	EE	Abhijit Prasad, D. M. H. Walker: Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors. DFT 2003: 140-
38	EE	Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi: CodSim -- A Combined Delay Fault Simulator. DFT 2003: 79-
37	EE	Wangqi Qiu, D. M. H. Walker: An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. ITC 2003: 592-601
36	EE	Wangqi Qiu, D. M. H. Walker: Testing the Path Delay Faults of ISCAS85 Circuit c6288. MTV 2003: 19-
35	EE	Sagar S. Sabade, D. M. H. Walker: Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification. VLSI Design 2003: 361-
34	EE	Sagar S. Sabade, D. M. H. Walker: Use of Multiple IDDQ Test Metrics for Outlier Identification. VTS 2003: 31-38
33	EE	Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker: A Circuit Level Fault Model for Resistive Opens and Bridges. VTS 2003: 379-384
32	EE	Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker: A circuit level fault model for resistive bridges. ACM Trans. Design Autom. Electr. Syst. 8(4): 546-559 (2003)
2002
31	EE	Sagar S. Sabade, D. M. H. Walker: Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis. DFT 2002: 381-389
30	EE	Sagar S. Sabade, D. M. H. Walker: Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. VLSI Design 2002: 755-760
29	EE	Sagar S. Sabade, D. M. H. Walker: Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. VTS 2002: 81-86
28	EE	Sagar S. Sabade, D. M. H. Walker: IDDQ Test: Will It Survive the DSM Challenge? IEEE Design & Test of Computers 19(5): 8-16 (2002)
2001
27	EE	Wanlin Cao, D. M. H. Walker, Rajarshi Mukherjee: An efficient solution to the storage correspondence problem for large sequential circuits. ASP-DAC 2001: 181-186
26		Hoki Kim, D. M. H. Walker, David Colby: A practical built-in current sensor for I_DDQ testing. ITC 2001: 405-414
25		Zoran Stanojevic, D. M. H. Walker: FedEx - a fast bridging fault extractor. ITC 2001: 696-703
24		Sagar S. Sabade, D. M. H. Walker: Improved wafer-level spatial analysis for I_DDQ limit setting. ITC 2001: 82-91
2000
23		Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler: Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. ITC 2000: 729-738
22	EE	Chul Young Lee, D. M. H. Walker: PROBE: A PPSFP Simulator for Resistive Bridging Faults. VTS 2000: 105-112
21	EE	Byungwoo Choi, D. M. H. Walker: Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. VTS 2000: 49-54
1999
20	EE	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi: IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs. Asian Test Symposium 1999: 375-
19		D. M. H. Walker: Design for Yield and Reliability is MORE Important Than DFT. ITC 1999: 1146
18		Vijay R. Sar-Dessai, D. M. H. Walker: Resistive bridge fault modeling, simulation and test generation. ITC 1999: 596-605
17	EE	Debashis Nayak, D. M. H. Walker: Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits. VTS 1999: 70-79
1998
16	EE	Vijay R. Sar-Dessai, D. M. H. Walker: Accurate Fault Modeling and Fault Simulation of Resistive Bridges. DFT 1998: 102-107
15	EE	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi: Bridging Fault Detection in FPGA Interconnects Using IDDQ. FPGA 1998: 95-104
14	EE	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi: Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ. ITC 1998: 1037-
13	EE	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi: IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays. IEEE Trans. Computers 47(10): 1136-1152 (1998)
1996
12		G. M. Luong, D. M. H. Walker: Test Generation for Global Delay Faults. ITC 1996: 433-442
11		Yuyun Liao, D. M. H. Walker: Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages. ITC 1996: 767-775
10	EE	Hari Balachandran, D. M. H. Walker: Improvement of SRAM-based failure analysis using calibrated Iddq testing. VTS 1996: 130-137
9	EE	Yuyun Liao, D. M. H. Walker: Optimal voltage testing for physically-based faults. VTS 1996: 344-353
1995
8		V. Ramakrishnan, D. M. H. Walker: IC Performance Prediction System. ITC 1995: 336-344
7		Young-Jun Kwon, D. M. H. Walker: Yiel Learning via Functional Test Data. ITC 1995: 626-635
1994
6	EE	Martin D. Giles, Duane S. Boning, Goodwin R. Chin, Walter C. Dietrich Jr., Michael S. Karasick, Mark E. Law, Purnendu K. Mozumder, Lee R. Nackman, V. T. Rajan, Duncan M. Hank Walker, Robert H. Wang, Alexander S. Wong: Semiconductor wafer representation for TCAD. IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 82-95 (1994)
1993
5	EE	Dinesh D. Gaitonde, Duncan M. Hank Walker: Test quality and yield analysis using the DEFAM defect to fault mapper. ICCAD 1993: 202-205
4	EE	D. M. H. Walker, Chris S. Kellen, David M. Svoboda, Andrzej J. Strojwas: The CDB/HCDB semiconductor wafer representation server. IEEE Trans. on CAD of Integrated Circuits and Systems 12(2): 283-295 (1993)
1991
3	EE	D. M. H. Walker, Chris S. Kellen, Andrzej J. Strojwas: A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator. DAC 1991: 579-584
1990
2	EE	Duncan M. Hank Walker, D. S. Nydick: DVLASIC: catastrophic fault yield simulation in a distributed processing environment. IEEE Trans. on CAD of Integrated Circuits and Systems 9(6): 655-664 (1990)
1986
1	EE	D. M. H. Walker, Stephen W. Director: VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 541-556 (1986)

Coauthor Index

1	Hari Balachandran	[10] [23] [47]
2	Duane S. Boning	[6]
3	Kenneth M. Butler	[23]
4	Wanlin Cao	[27]
5	Goodwin R. Chin	[6]
6	Byungwoo Choi	[21]
7	David Colby	[26]
8	Walter C. Dietrich Jr.	[6]
9	Stephen W. Director	[1]
10	Stefan Eichenberger	[56]
11	Steve Fancler	[51]
12	Dinesh D. Gaitonde	[5]
13	Martin D. Giles	[6]
14	Guido Gronthoud	[56]
15	Kanupriya Gulati	[57]
16	Nikhil Jayakumar	[57]
17	Michael S. Karasick	[6]
18	Chris S. Kellen	[3] [4]
19	Sunil P. Khatri	[57]
20	Hoki Kim	[26]
21	Hyun Sung Kim	[55]
22	Bram Kruseman	[56]
23	Young-Jun Kwon	[7]
24	Fred Lakbani	[23]
25	Mark E. Law	[6]
26	Chul Young Lee	[22]
27	Zhuo Li	[32] [33] [38] [44] [46] [47] [48] [49] [50]
28	Yuyun Liao	[9] [11]
29	Fabrizio Lombardi	[13] [14] [15] [20]
30	Xiang Lu	[32] [33] [38] [44] [46] [48] [49] [50] [51] [56]
31	G. M. Luong	[12]
32	Ananta K. Majhi	[56]
33	Purnendu K. Mozumder	[6]
34	Rajarshi Mukherjee	[27]
35	Lee R. Nackman	[6]
36	Debashis Nayak	[17]
37	D. S. Nydick	[2]
38	Abhijit Prasad	[39]
39	Wangqi Qiu	[32] [33] [36] [37] [38] [44] [46] [47] [48] [49] [50] [51]
40	V. T. Rajan	[6]
41	V. Ramakrishnan	[8]
42	Divya Reddy	[47]
43	Sagar S. Sabade	[24] [28] [29] [30] [31] [34] [35] [40] [41] [42] [43] [45] [54]
44	Vijay R. Sar-Dessai	[16] [18]
45	Jayashree Saxena	[23]
46	Weiping Shi	[32] [33] [38] [44] [46] [47] [48] [49] [50] [51]
47	Zoran Stanojevic	[23] [25]
48	Andrzej J. Strojwas	[3] [4]
49	David M. Svoboda	[4]
50	Luis Elvira Villagra	[56]
51	Jing Wang	[44] [47] [51] [56]
52	Robert H. Wang	[6]
53	Zheng Wang	[58]
54	Paul J. A. M. van de Wiel	[56]
55	Alexander S. Wong	[6]
56	Lei Wu	[53]
57	Bin Xue	[52]
58	Ziding Yue	[51]
59	Lan Zhao	[13] [14] [15] [20]

Colors in the list of coauthors