2006 |
16 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
A Gated Clock Scheme for Low Power Testing of Logic Cores.
J. Electronic Testing 22(1): 89-99 (2006) |
2004 |
15 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains.
DATE 2004: 62-67 |
14 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains.
DELTA 2004: 287-294 |
13 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
Power-Driven Routing-Constrained Scan Chain Design.
J. Electronic Testing 20(6): 647-660 (2004) |
2003 |
12 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.
ITC 2003: 488-493 |
2002 |
11 | EE | Loïs Guiller,
Frederic Neuveux,
S. Duggirala,
R. Chandramouli,
Rohit Kapur:
Integrating DFT in the Physical Synthesis Flow.
ITC 2002: 788-795 |
2001 |
10 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.
Asian Test Symposium 2001: 253-258 |
9 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan-Based BIST.
IOLTW 2001: 87-89 |
8 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Hans-Joachim Wunderlich:
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.
VTS 2001: 306-311 |
2000 |
7 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
An adjacency-based test pattern generator for low power BIST design.
Asian Test Symposium 2000: 459-464 |
6 | | Patrick Girard,
Christian Landrault,
Loïs Guiller,
Serge Pravossoudovitch:
Low power BIST design by hypergraph partitioning: methodology and architectures.
ITC 2000: 652-661 |
5 | EE | Salvador Manich,
A. Gabarró,
M. Lopez,
Joan Figueras,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
P. Teixeira,
M. Santos:
Low Power BIST by Filtering Non-Detecting Vectors.
J. Electronic Testing 16(3): 193-202 (2000) |
1999 |
4 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.
Asian Test Symposium 1999: 89-94 |
3 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.
Great Lakes Symposium on VLSI 1999: 24- |
2 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Joan Figueras,
Salvador Manich,
P. Teixeira,
M. Santos:
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.
ISCAS (1) 1999: 110-113 |
1 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
A Test Vector Inhibiting Technique for Low Energy BIST Design.
VTS 1999: 407-412 |