| 2003 |
|---|
| 13 | EE | Peter Dahlgren,
Paul Dickinson,
Ishwar Parulkar:
Latch Divergency In Microprocessor Failure Analysis.
ITC 2003: 755-763 |
| 1998 |
|---|
| 12 | EE | Peter Dahlgren:
Switch-level bridging fault simulation in the presence of feedbacks.
ITC 1998: 363-371 |
| 1997 |
|---|
| 11 | EE | Peter Dahlgren:
Switch-level modeling of feedback faults using global oscillation control.
VTS 1997: 117-122 |
| 1996 |
|---|
| 10 | EE | Peter Dahlgren:
Oscillation Control in Logic Simulation using Dynamic Dominance Grahps.
DAC 1996: 155-160 |
| 9 | EE | Peter Dahlgren,
Peter Lidén:
A fault model for switch-level simulation of gate-to-drain shorts.
VTS 1996: 414-421 |
| 1995 |
|---|
| 8 | | Peter Dahlgren,
Peter Lidén:
A Switch-level Algorithm for Simulation of Transients in Combinational Logic.
FTCS 1995: 207-216 |
| 7 | EE | Peter Dahlgren:
A multiple-dominance switch-level model for simulation of short faults.
ICCAD 1995: 674-680 |
| 6 | | Peter Lidén,
Peter Dahlgren:
Coverage of Transistor-Level and Gate-Level Stuck-at Faults in CMOS Checkers.
ISCAS 1995: 2124-2127 |
| 5 | EE | Peter Lidén,
Peter Dahlgren:
Switch-level modeling of transistor-level stuck-at faults.
VTS 1995: 208-215 |
| 1994 |
|---|
| 4 | EE | Peter Dahlgren,
Peter Lidén:
Modeling of Intermediate Node States in switch-Level Networks.
DAC 1994: 722-727 |
| 3 | | Peter Lidén,
Peter Dahlgren,
Rolf Johansson,
Johan Karlsson:
On Latching Probability of Particle Induced Transients in Combinational Networks.
FTCS 1994: 340-349 |
| 1993 |
|---|
| 2 | EE | Peter Dahlgren,
Peter Lidén:
Efficient modeling of switch-level networks containing undetermined logic node states.
ICCAD 1993: 746-752 |
| 1992 |
|---|
| 1 | | Peter Lidén,
Peter Dahlgren,
Jan Torin:
Transistor Fault Coverage for Self-Testing CMOS Checkers.
ITC 1992: 476-485 |
