| 2009 |
|---|
| 8 | EE | Ramamurthy Vishweshwara,
Ramakrishnan Venkatraman,
H. Udayakumar,
N. V. Arvind:
An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis.
VLSI Design 2009: 519-524 |
| 2008 |
|---|
| 7 | EE | Bishnu Prasad Das,
Janakiraman V. Bharadwaj Amrutur,
H. S. Jamadagni,
N. V. Arvind:
Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations.
VLSI Design 2008: 685-691 |
| 2006 |
|---|
| 6 | EE | K. A. Rajagopal,
R. Sivakumar,
N. V. Arvind,
C. Sreeram,
Vish Visvanathan,
Shailendra Dhuri,
Roopesh Chander,
Patrick Fortner,
Subra Sripada,
Qiuyang Wu:
A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff.
VLSI Design 2006: 277-282 |
| 2004 |
|---|
| 5 | EE | Sachin Shrivastava,
Dhanoop Varghese,
Vikas Narang,
N. V. Arvind:
Improved Approach for Noise Propagation to Identify Functional Noise Violations.
VLSI Design 2004: 705-708 |
| 4 | EE | N. V. Arvind,
K. A. Rajagopal,
H. S. Ajith,
Das Suparna:
Path Based Approach for Crosstalk Delay Analysis.
VLSI Design 2004: 727-730 |
| 2003 |
|---|
| 3 | EE | Clive Bittlestone,
Anthony M. Hill,
Vipul Singhal,
N. V. Arvind:
Architecting ASIC libraries and flows in nanometer era.
DAC 2003: 776-781 |
| 2 | EE | Jayashree Saxena,
Kenneth M. Butler,
Vinay B. Jayaram,
Subhendu Kundu,
N. V. Arvind,
Pravin Sreeprakash,
Manfred Hachinger:
A Case Study of IR-Drop in Structured At-Speed Testing.
ITC 2003: 1098-1104 |
| 2001 |
|---|
| 1 | EE | N. V. Arvind,
P. R. Suresh,
V. Sivakumar,
Chandrani Pal,
Debaprasad Das:
Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs.
VLSI Design 2001: 518-523 |
