Yoshihito Nishizaki

List of publications from the DBLP Bibliography Server - FAQ

2005

3 EE Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi: Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. Asian Test Symposium 2005: 156-161

2003

2 EE Yoshihito Nishizaki, Osamu Nakayama, Chiaki Matsumoto, Yoshitaka Kimura, Toshimi Kobayashi, Hiroyuki Nakamura: Testing DSM ASIC With Static, \DeltaIDDQ, And Dynamic Test Suite: Implementation And Results. ITC 2003: 85-94

1990

1 EE Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Logic Synthesis for Programmable Gate Arrays. DAC 1990: 620-625

2005
3	EE	Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi: Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. Asian Test Symposium 2005: 156-161
2003
2	EE	Yoshihito Nishizaki, Osamu Nakayama, Chiaki Matsumoto, Yoshitaka Kimura, Toshimi Kobayashi, Hiroyuki Nakamura: Testing DSM ASIC With Static, \DeltaIDDQ, And Dynamic Test Suite: Implementation And Results. ITC 2003: 85-94
1990
1	EE	Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Logic Synthesis for Programmable Gate Arrays. DAC 1990: 620-625

Coauthor Index

1	Robert K. Brayton	[1]
2	Vivek Chickermane	[3]
3	Brion L. Keller	[3]
4	Yoshitaka Kimura	[2]
5	Toshimi Kobayashi	[2]
6	Chiaki Matsumoto	[2]
7	Rajeev Murgai	[1]
8	Hiroyuki Nakamura	[2] [3]
9	Osamu Nakayama	[2]
10	Alberto L. Sangiovanni-Vincentelli	[1]
11	Narendra V. Shenoy	[1]
12	Akio Shirokane	[3]
13	Yoshihiko Terauchi	[3]
14	Tsutomu Ube	[3]
15	Anis Uzzaman	[3]