2008 | ||
---|---|---|
41 | EE | Amir Zjajo, José Pineda de Gyvez: Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters. DATE 2008: 74-79 |
40 | EE | Amir Zjajo, Shaji Krishnan, José Pineda de Gyvez: Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm. DDECS 2008: 287-292 |
39 | EE | Amir Zjajo, José Pineda de Gyvez: Calibration and Debugging of Multi-step Analog to Digital Converters. DELTA 2008: 512-515 |
2007 | ||
38 | EE | Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez: Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. DATE 2007: 1301-1306 |
2006 | ||
37 | EE | Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez: Testing and Diagnosis of Power Switches in SOCs. European Test Symposium 2006: 145-150 |
36 | EE | Amir Zjajo, José Pineda de Gyvez, Guido Gronthoud: Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits. J. Electronic Testing 22(4-6): 399-409 (2006) |
35 | EE | Josep Rius, Maurice Meijer, José Pineda de Gyvez: An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. J. Low Power Electronics 2(1): 80-86 (2006) |
2005 | ||
34 | EE | Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez: Limits to performance spread tuning using adaptive voltage and body biasing. ISCAS (1) 2005: 5-8 |
33 | EE | Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez: Glitch-free discretely programmable clock generation on chip. ISCAS (2) 2005: 1839-1842 |
32 | EE | Maurice Meijer, José Pineda de Gyvez, Ralph Otten: On-chip digital power supply control for system-on-chip applications. ISLPED 2005: 311-314 |
31 | EE | Josep Rius, José Pineda de Gyvez, Maurice Meijer: An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. PATMOS 2005: 187-196 |
30 | EE | José Pineda de Gyvez, Guido Gronthoud, Rashid Amine: Multi-VDD Testing for Analog Circuits. J. Electronic Testing 21(3): 311-322 (2005) |
2004 | ||
29 | EE | Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek: Low energy FPGA interconnect design. ACM Great Lakes Symposium on VLSI 2004: 393-396 |
28 | EE | Josep Rius Vázquez, José Pineda de Gyvez: Power Supply Noise Monitor for Signal Integrity Faults. DATE 2004: 1406-1407 |
27 | EE | Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek: Low energy FPGA interconnect design. FPGA 2004: 255 |
26 | EE | Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez: Technology exploration for adaptive power and frequency scaling in 90nm CMOS. ISLPED 2004: 14-19 |
25 | EE | Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez: AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. ITC 2004: 1006-1015 |
24 | EE | José Pineda de Gyvez, Guido Gronthoud, Cristiano Cenci, Martin Posch, Thomas Burger, Manfred Koller: Power Supply Ramping for Quasi-static Testing of PLLs. ITC 2004: 980-987 |
23 | EE | Rohini Krishnan, José Pineda de Gyvez: Low Energy Switch Block For FPGAs. VLSI Design 2004: 209-214 |
22 | EE | Josep Rius Vázquez, José Pineda de Gyvez: Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs. VTS 2004: 53-58 |
2003 | ||
21 | EE | Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick: Encoded-Low Swing Technique for Ultra Low Power Interconnect. FPL 2003: 240-251 |
20 | EE | José Pineda de Gyvez, Guido Gronthoud, Rashid Amine: VDD Ramp Testing for RF Circuits. ITC 2003: 651-658 |
19 | EE | Antonio F. Mondragón-Torres, Terry Mayhugh Jr., José Pineda de Gyvez, José Silva-Martínez, Edgar Sánchez-Sinencio: An Analog Integrated Circuit Design Laboratory. MSE 2003: 91-92 |
18 | EE | José Pineda de Gyvez, Rosa Rodríguez-Montañés: Threshold Voltage Mismatch (DeltaVT) Fault Modeling. VTS 2003: 145-150 |
17 | EE | Phillip Christie, José Pineda de Gyvez: Prelayout interconnect yield prediction. IEEE Trans. VLSI Syst. 11(1): 55-59 (2003) |
2002 | ||
16 | EE | Rosa Rodríguez-Montañés, Paul Volf, José Pineda de Gyvez: Resistance Characterization for Weak Open Defects. IEEE Design & Test of Computers 19(5): 18-26 (2002) |
2001 | ||
15 | EE | José Pineda de Gyvez: Yield modeling and BEOL fundamentals. SLIP 2001: 135-163 |
14 | EE | Phillip Christie, José Pineda de Gyvez: Pre-layout prediction of interconnect manufacturability. SLIP 2001: 167-173 |
13 | EE | José Pineda de Gyvez, Eric van de Wetering: Average Leakage Current Estimation of CMOS Logic Circuits. VTS 2001: 375-379 |
2000 | ||
12 | EE | Madhuban Kishor, José Pineda de Gyvez: Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families. DFT 2000: 349-357 |
1999 | ||
11 | EE | O. A. Gonzalez, Gunhee Han, José Pineda de Gyvez, Edgar Sánchez-Sinencio: CMOS cryptosystem using a Lorenz chaotic oscillator. ISCAS (5) 1999: 442-445 |
10 | EE | A. Dornbusch, José Pineda de Gyvez: Chaotic generation of PN sequences: a VLSI implementation. ISCAS (5) 1999: 454-457 |
1998 | ||
9 | EE | Lei Wang, José Pineda de Gyvez, Edgar Sánchez-Sinencio: Time multiplexed color image processing based on a CNN with cell-state outputs. IEEE Trans. VLSI Syst. 6(2): 314-322 (1998) |
1996 | ||
8 | EE | Apollo Q. Fong, Ajay Kanji, José Pineda de Gyvez: Time-Multiplexing Scheme for Cellular Neural Networks Based Image Processing. Real-Time Imaging 2(4): 231-239 (1996) |
1995 | ||
7 | Apollo Q. Fong, Ajay Kanji, Edgar Sánchez-Sinencio, José Pineda de Gyvez: A Universal Interface Between PC and Neural Networks Hardware. ISCAS 1995: 1169-1172 | |
6 | Oscar Moreira-Tamayo, José Pineda de Gyvez: Time Domain Analog Wavelet Transform in Real-Time. ISCAS 1995: 1640-1643 | |
1994 | ||
5 | Chi-Chien Lee, José Pineda de Gyvez: Single-Layer CNN Simulator. ISCAS 1994: 217-220 | |
4 | John Willis, José Pineda de Gyvez: Behavioral Testing of Cellular Neural Networks. ISCAS 1994: 229-232 | |
3 | Chi-Chien Lee, José Pineda de Gyvez: Time-Mulitplexing CNN Simulator. ISCAS 1994: 407-410 | |
1992 | ||
2 | EE | José Pineda de Gyvez, Chennian Di: IC defect sensitivity for footprint-type spot defects. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 638-658 (1992) |
1989 | ||
1 | EE | José Pineda de Gyvez, Jochen A. G. Jess: On the design and implementation of a wafer yield editor. IEEE Trans. on CAD of Integrated Circuits and Systems 8(8): 920-925 (1989) |