| 2006 |
|---|
| 13 | EE | Ramesh C. Tekumalla:
An On-Chip Diagnosis Methodology for Embedded Cores with Replaceable Modules.
VLSI Design 2006: 824-827 |
| 2003 |
|---|
| 12 | EE | Ramesh C. Tekumalla:
On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures.
ITC 2003: 737-744 |
| 2002 |
|---|
| 11 | EE | Ramesh C. Tekumalla,
Scott Davidson:
On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis.
ITC 2002: 993-1002 |
| 2001 |
|---|
| 10 | EE | Ramesh C. Tekumalla,
Srikanth Venkataraman,
Jayabrata Ghosh-Dastidar:
On Diagnosing Path Delay Faults in an At-Speed Environment.
VTS 2001: 28-33 |
| 9 | EE | Ramesh C. Tekumalla,
Premachandran R. Menon:
Identification of primitive faults in combinational and sequentialcircuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1426-1442 (2001) |
| 2000 |
|---|
| 8 | EE | Ramesh C. Tekumalla:
On Test Set Generation for Efficient Path Delay Fault Diagnosis.
VTS 2000: 343-348 |
| 7 | EE | Ramesh C. Tekumalla,
Premachandran R. Menon:
On Redundant Path Delay Faults in Synchronous Sequential Circuits.
IEEE Trans. Computers 49(3): 277-282 (2000) |
| 1999 |
|---|
| 6 | | Ramesh C. Tekumalla,
Premachandran R. Menon:
Robust testability of primitive faults using test points.
ITC 1999: 260-268 |
| 1998 |
|---|
| 5 | EE | Ramesh C. Tekumalla,
Premachandran R. Menon:
On primitive fault test generation in non-scan sequential circuits.
ICCAD 1998: 275-282 |
| 1997 |
|---|
| 4 | EE | Ramesh C. Tekumalla,
Premachandran R. Menon:
Test generation for primitive path delay faults in combinational circuits.
ICCAD 1997: 636-641 |
| 3 | | Ramesh C. Tekumalla,
Premachandran R. Menon:
Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan.
ICCD 1997: 648-653 |
| 2 | | Ramesh C. Tekumalla,
Premachandran R. Menon:
Delay Testing with Clock Control: An Alternative to Enhanced Scan.
ITC 1997: 454-462 |
| 1996 |
|---|
| 1 | EE | Ramesh C. Tekumalla,
Premachandran R. Menon:
Identifying Redundant Path Delay Faults in Sequential Circuits.
VLSI Design 1996: 406-411 |
