| 2003 |
|---|
| 7 | EE | Theo J. Powell,
Wu-Tung Cheng,
Joseph Rayhawk,
Omer Samman,
Paul Policke,
Sherry Lai:
BIST for Deep Submicron ASIC Memories with High Performance Application.
ITC 2003: 386-392 |
| 2002 |
|---|
| 6 | EE | Yu Huang,
Sudhakar M. Reddy,
Wu-Tung Cheng,
Paul Reuter,
Nilanjan Mukherjee,
Chien-Chung Tsai,
Omer Samman,
Yahya Zaidan:
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.
ITC 2002: 74-82 |
| 5 | EE | Yu Huang,
Nilanjan Mukherjee,
Chien-Chung Tsai,
Omer Samman,
Yahya Zaidan,
Yanping Zhang,
Wu-Tung Cheng,
Sudhakar M. Reddy:
Constraint Driven Pin Mapping for Concurrent SOC Testing.
VLSI Design 2002: 511-516 |
| 4 | EE | Yu Huang,
Chien-Chung Tsai,
Nilanjan Mukherjee,
Omer Samman,
Wu-Tung Cheng,
Sudhakar M. Reddy:
Synthesis of Scan Chains for Netlist Descriptions at RT-Level.
J. Electronic Testing 18(2): 189-201 (2002) |
| 3 | EE | Yu Huang,
Wu-Tung Cheng,
Chien-Chung Tsai,
Nilanjan Mukherjee,
Omer Samman,
Yahya Zaidan,
Sudhakar M. Reddy:
On Concurrent Test of Core-Based SOC Design.
J. Electronic Testing 18(4-5): 401-414 (2002) |
| 2001 |
|---|
| 2 | EE | Yu Huang,
Wu-Tung Cheng,
Chien-Chung Tsai,
Nilanjan Mukherjee,
Omer Samman,
Yahya Zaidan,
Sudhakar M. Reddy:
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.
Asian Test Symposium 2001: 265- |
| 1 | | Yu Huang,
Chien-Chung Tsai,
Neelanjan Mukherjee,
Omer Samman,
Dan Devries,
Wu-Tung Cheng,
Sudhakar M. Reddy:
On RTL scan design.
ITC 2001: 728-737 |
