2008 | ||
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49 | EE | Mani Soma: Enhancing industry participation in ISCAS and Circuits and Systems Society. ISCAS 2008 |
48 | EE | Apurva Mishra, Mani Soma: A Time-Domain Method for Pseudo-Spectral Characterization. VTS 2008: 163-168 |
2007 | ||
47 | EE | Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma: An On-Chip Delta-Time-to-Voltage Converter for Real-Time Measurement of Clock Jitter. ISCAS 2007: 2798-2801 |
2006 | ||
46 | EE | Qi Wang, Mani Soma: RF Front-end System Gain and Linearity Built-in Test. VTS 2006: 228-233 |
2005 | ||
45 | David Bordoley, Hieu Nguyen, Mani Soma: A statistical study of the effectiveness of BIST jitter measurement techniques. ICCAD 2005: 100-107 | |
2004 | ||
44 | EE | Bryan Nelson, Mani Soma: On-chip calibration technique for delay line based BIST jitter measurement. ISCAS (1) 2004: 944-947 |
43 | EE | Takahiro J. Yamaguchi, Masahiro Ishida, Kiyotaka Ichiyama, Mani Soma, Christian Krawinkel, Katsuaki Ohsawa, Masao Sugai: A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems. ITC 2004: 77-84 |
42 | EE | Karen Taylor, Bryan Nelson, Alan Chong, Hieu Nguyen, Henry C. Lin, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz: Experimental Results for High-Speed Jitter Measurement Technique. ITC 2004: 85-94 |
41 | EE | Qi Wang, Yi Tang, Mani Soma: GHz RF Front-end Bandwidth Time Domain Measurement. VTS 2004: 223-228 |
40 | EE | Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida: Skew measurements in clock distribution circuits using an analytic signal method. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 997-1009 (2004) |
2003 | ||
39 | EE | Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Makoto Kurosawa, Hirobumi Musha: Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements. ITC 2003: 58-66 |
38 | EE | Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz: CMOS Built-In Test Architecture for High-Speed Jitter Measurement. ITC 2003: 67-76 |
37 | EE | Mani Soma, Welela Haileselassie, Jessica Sherrid: Measurement of Phase and Frequency Variations in Radio-Frequency Signal. VTS 2003: 203-208 |
36 | EE | Kianosh Rahimi, Mani Soma: Layout driven synthesis of multiple scan chains. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 317-326 (2003) |
35 | EE | Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha: Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division. J. Electronic Testing 19(2): 183-193 (2003) |
2002 | ||
34 | EE | Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Hirobumi Musha: Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices. Asian Test Symposium 2002: 45-48 |
33 | EE | Mani Soma, Welela Haileselassie, Jessica Yan, Rajesh Raina: A Wavelet-Based Timing Parameter Extraction Method. ITC 2002: 120-128 |
32 | EE | Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Hirobumi Musha, Louis Malarsie: A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter. ITC 2002: 717-725 |
31 | EE | Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha: Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division. VTS 2002: 207-212 |
2001 | ||
30 | EE | Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida: Testing clock distribution circuits using an analytic signal method. ITC 2001: 323-331 |
29 | Seongwon Kim, Mani Soma: Test evaluation and data on defect-oriented BIST architecture for high-speed PLL. ITC 2001: 830-837 | |
28 | EE | Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, David Halter, Rajesh Raina, Jim Nissen: A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals. VTS 2001: 102-110 |
27 | EE | Henry Chang, Steve Dollens, Gordon Roberts, Charles E. Stroud, Mani Soma, Jacob A. Abraham: Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? VTS 2001: 415-416 |
26 | EE | Mani Soma, Sam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg: Hierarchical ATPG for Analog Circuits and Systems. IEEE Design & Test of Computers 18(1): 72-81 (2001) |
2000 | ||
25 | Takahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe: Jitter measurements of a PowerPCTM microprocessor using an analytic signal method. ITC 2000: 955-964 | |
24 | EE | Seongwon Kim, Mani Soma, Dilip Risbud: An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops. VTS 2000: 231-236 |
23 | EE | Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Toshifumi Watanabe, Tadahiro Ohmi: Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method. VTS 2000: 395-402 |
1999 | ||
22 | EE | Sam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg, Mani Soma: Efficient Test Set Design for Analog and Mixed-Signal Circuits and Systems. Asian Test Symposium 1999: 239- |
21 | Mani Soma: Panel Statement: Increasing test coverage in a VLSI design course. ITC 1999: 1136 | |
20 | Cecilia Metra, Flavio Giovanelli, Mani Soma, Bruno Riccò: Self-checking scheme for very fast clocks' skew correction. ITC 1999: 652-661 | |
19 | EE | Jinyan Zhang, Sam D. Huynh, Mani Soma: A Test Point Insertion Algorithm for Mixed-Signal Circuits. VTS 1999: 319-325 |
18 | EE | Giri Devarayanadurg, Mani Soma, Prashant Goteti, Sam D. Huynh: Test set selection for structural faults in analog IC's. IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 1026-1039 (1999) |
1998 | ||
17 | EE | Sam D. Huynh, Seongwon Kim, Mani Soma, Jinyan Zhang: Dynamic Test Set Generation for Analog Circuits and Systems. Asian Test Symposium 1998: 360-365 |
16 | EE | Sam D. Huynh, Seongwon Kim, Mani Soma, Jinyan Zhang: Testability analysis and multi-frequency ATPG for analog circuits and systems. ICCAD 1998: 376-383 |
15 | EE | Mani Soma: Mixed-signal on-chip timing measurements. Integration 26(1-2): 151-165 (1998) |
1997 | ||
14 | Bozena Kaminska, Karim Arabi, I. Bell, José L. Huertas, B. Kim, Adoración Rueda, Mani Soma, Prashant Goteti: Analog and Mixed-Signal Benchmark Circuits-First Release. ITC 1997: 183-190 | |
13 | Takahiro J. Yamaguchi, Mani Soma: Dynamic Testing of ADCs Using Wavelet Transforms. ITC 1997: 379-388 | |
12 | Thomas M. Bocek, Tuyen D. Vu, Mani Soma, Jason D. Moffatt: Experimental Results for Current-Based Analog Scan. ITC 1997: 768-775 | |
11 | EE | Yong Je Lim, Mani Soma: Statistical estimation of delay-dependent switching activities in embedded CMOS combinational circuits. IEEE Trans. VLSI Syst. 5(3): 309-319 (1997) |
1996 | ||
10 | EE | Yong Je Lim, Kyung-Im Son, Heung-Joon Park, Mani Soma: A Statistical Approach to the Estimation of Delay Dependent Switching Activities in CMOS Combinational Circuits. DAC 1996: 445-450 |
9 | Giri Devarayanadurg, Prashant Goteti, Mani Soma: Hierarchy Based Statistical Fault Simulation of Mixed-Signal ICs. ITC 1996: 521-527 | |
1995 | ||
8 | EE | Giri Devarayanadurg, Mani Soma: Dynamic test signal design for analog ICs. ICCAD 1995: 627-630 |
1994 | ||
7 | EE | Giri Devarayanadurg, Mani Soma: Analytical fault modeling and static test generation for analog ICs. ICCAD 1994: 44-47 |
1993 | ||
6 | Mani Soma: Fault Coverage of DC Parametric Tests for Embedded Analog Amplifiers. ITC 1993: 566-573 | |
5 | Anchada Charoenrook, Mani Soma: Fault Diagnosis of Flash ADC using DNL Test. ITC 1993: 680-689 | |
4 | EE | Mani Soma: Guest editor's introduction. J. Electronic Testing 4(4): 297-298 (1993) |
1992 | ||
3 | Mani Soma: Guest Editor's Introduction: Mixing Analog and Digital Systems. IEEE Design & Test of Computers 9(1): 6-7 (1992) | |
1988 | ||
2 | Mehdi Katoozi, Mani Soma: A BIST Design of Structured Arrays with Fault-Tolerant Layout. ITC 1988: 514-521 | |
1 | William H. Nicholls, Mani Soma: Fault Bundling: Reducing Machine Evaluation Activity in Hierarchical Concurrent Fault Simulation. ITC 1988: 569-573 |