2008 |
25 | EE | Cecilia Metra,
Martin Omaña,
T. M. Mak,
Asifur Rahman,
Simon Tam:
Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors.
DFT 2008: 465-473 |
24 | EE | Daniele Rossi,
Martin Omaña,
Cecilia Metra:
Checkers' No-Harm Alarms and Design Approaches to Tolerate Them.
J. Electronic Testing 24(1-3): 93-103 (2008) |
2007 |
23 | EE | Cecilia Metra,
Martin Omaña,
T. M. Mak,
Simon Tam:
Novel Approach to Clock Fault Testing for High Performance Microprocessors.
VTS 2007: 441-446 |
22 | EE | Martin Omaña,
Daniele Rossi,
Cecilia Metra:
Latch Susceptibility to Transient Faults and New Hardening Approach.
IEEE Trans. Computers 56(9): 1255-1268 (2007) |
2006 |
21 | EE | Martin Omaña,
José Manuel Cazeaux,
Daniele Rossi,
Cecilia Metra:
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects.
DATE 2006: 170-175 |
20 | | Cecilia Metra,
Daniele Rossi,
Martin Omaña,
José Manuel Cazeaux,
T. M. Mak:
Can Clock Faults be Detected Through Functional Test?
DDECS 2006: 168-173 |
19 | EE | Cecilia Metra,
Martin Omaña,
Daniele Rossi,
José Manuel Cazeaux,
T. M. Mak:
Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation.
IOLTS 2006: 17-22 |
18 | EE | Daniele Rossi,
Martin Omaña,
Cecilia Metra,
Andrea Pagni:
Checker No-Harm Alarm Robustness.
IOLTS 2006: 275-280 |
2005 |
17 | EE | Cecilia Metra,
Martin Omaña,
Daniele Rossi,
José Manuel Cazeaux,
T. M. Mak:
The Other Side of the Timing Equation: a Result of Clock Faults.
DFT 2005: 169-177 |
16 | EE | Daniele Rossi,
Martin Omaña,
Fabio Toma,
Cecilia Metra:
Multiple Transient Faults in Logic: An Issue for Next Generation ICs.
DFT 2005: 352-360 |
15 | EE | Martin Omaña,
O. Losco,
Cecilia Metra,
Andrea Pagni:
On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization.
IOLTS 2005: 163-168 |
14 | EE | José Manuel Cazeaux,
Daniele Rossi,
Martin Omaña,
Cecilia Metra,
Abhijit Chatterjee:
On Transistor Level Gate Sizing for Increased Robustness to Transient Faults.
IOLTS 2005: 23-28 |
13 | EE | Martin Omaña,
Daniele Rossi,
Cecilia Metra:
Low Cost Scheme for On-Line Clock Skew Compensation.
VTS 2005: 90-95 |
12 | EE | Martin Omaña,
Daniele Rossi,
Cecilia Metra:
Low Cost and High Speed Embedded Two-Rail Code Checker.
IEEE Trans. Computers 54(2): 153-164 (2005) |
2004 |
11 | EE | Cecilia Metra,
T. M. Mak,
Martin Omaña:
Fault secureness need for next generation high performance microprocessor design for testability structures.
Conf. Computing Frontiers 2004: 444-450 |
10 | EE | Cecilia Metra,
T. M. Mak,
Martin Omaña:
Are Our Design for Testability Features Fault Secure?
DATE 2004: 714-715 |
9 | EE | Martin Omaña,
Daniele Rossi,
Cecilia Metra:
Fast and Low-Cost Clock Deskew Buffer.
DFT 2004: 202-210 |
8 | EE | Cecilia Metra,
A. Ferrari,
Martin Omaña,
Andrea Pagni:
Hardware Reconfiguration Scheme for High Availability Systems.
IOLTS 2004: 161-166 |
7 | EE | José Manuel Cazeaux,
Martin Omaña,
Cecilia Metra:
Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop.
IOLTS 2004: 17-24 |
6 | EE | Cecilia Metra,
T. M. Mak,
Martin Omaña:
Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing.
ITC 2004: 1223-1231 |
5 | EE | Martin Omaña,
Daniele Rossi,
Cecilia Metra:
Model for Transient Fault Susceptibility of Combinational Circuits.
J. Electronic Testing 20(5): 501-509 (2004) |
2003 |
4 | EE | Martin Omaña,
Daniele Rossi,
Cecilia Metra:
High Speed and Highly Testable Parallel Two-Rail Code Checker.
DATE 2003: 10608-10615 |
3 | EE | Cecilia Metra,
Stefano Di Francescantonio,
Martin Omaña:
Automatic Modification of Sequential Circuits for Self-Checking Implementation.
DFT 2003: 417-424 |
2 | EE | Martin Omaña,
Giacinto Papasso,
Daniele Rossi,
Cecilia Metra:
A Model for Transient Fault Propagation in Combinatorial Logic.
IOLTS 2003: 111- |
1 | EE | Martin Omaña,
Daniele Rossi,
Cecilia Metra:
Novel Transient Fault Hardened Static Latch.
ITC 2003: 886-892 |