| 2009 |
|---|
| 256 | EE | Suraj Sindia,
Virendra Singh,
Vishwani D. Agrawal:
Polynomial coefficient based DC testing of non-linear analog circuits.
ACM Great Lakes Symposium on VLSI 2009: 69-74 |
| 255 | EE | Fan Wang,
Vishwani D. Agrawal:
Soft Error Rates with Inertial and Logical Masking.
VLSI Design 2009: 459-464 |
| 254 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 25(1): 1 (2009) |
| 2008 |
|---|
| 253 | EE | Vishwani D. Agrawal:
A tutorial on test power.
ISLPED 2008: 237-238 |
| 252 | EE | Fan Wang,
Vishwani D. Agrawal:
Single Event Upset: An Embedded Tutorial.
VLSI Design 2008: 429-434 |
| 251 | EE | Yuanlin Lu,
Vishwani D. Agrawal:
Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation.
VLSI Design 2008: 527-532 |
| 250 | EE | Rajamani Sethuram,
Michael L. Bushnell,
Vishwani D. Agrawal:
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults.
VTS 2008: 329-335 |
| 249 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 24(1-3): 1 (2008) |
| 248 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 24(4): 321 (2008) |
| 247 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 24(5): 421 (2008) |
| 246 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 24(6): 505-506 (2008) |
| 2007 |
|---|
| 245 | EE | Yuanlin Lu,
Vishwani D. Agrawal:
Statistical Leakage and Timing Optimization for Submicron Process Variation.
VLSI Design 2007: 439-444 |
| 244 | EE | Nitin Yogi,
Vishwani D. Agrawal:
Spectral RTL Test Generation for Microprocessors.
VLSI Design 2007: 473-478 |
| 243 | EE | Kalyana R. Kantipudi,
Vishwani D. Agrawal:
A Reduced Complexity Algorithm for Minimizing N-Detect Tests.
VLSI Design 2007: 492-497 |
| 242 | EE | Soumitra Bose,
Vishwani D. Agrawal:
Delay Test Quality Evaluation Using Bounded Gate Delays.
VTS 2007: 23-28 |
| 241 | EE | Lan Rao,
Michael L. Bushnell,
Vishwani D. Agrawal:
Graphical IDDQ Signatures Reduce Defect Level and Yield Loss.
IEEE Trans. VLSI Syst. 15(11): 1245-1255 (2007) |
| 240 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 23(1): 5 (2007) |
| 239 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 23(2-3): 111 (2007) |
| 238 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 23(5): 369 (2007) |
| 237 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 23(6): 465 (2007) |
| 2006 |
|---|
| 236 | EE | Fei Hu,
Vishwani D. Agrawal:
Input-specific dynamic power optimization for VLSI circuits.
ISLPED 2006: 232-237 |
| 235 | EE | Vishwani D. Agrawal,
Soumitra Bose,
Vijay Gangaram:
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring.
VTS 2006: 88-93 |
| 234 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 22(1): 5 (2006) |
| 233 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 22(2): 111 (2006) |
| 232 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 22(4-6): 307 (2006) |
| 231 | EE | Tezaswi Raja,
Vishwani D. Agrawal,
Michael L. Bushnell:
Transistor Sizing of Logic Gates to Maximize Input Delay Variability.
J. Low Power Electronics 2(1): 121-128 (2006) |
| 230 | EE | Yuanlin Lu,
Vishwani D. Agrawal:
CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff.
J. Low Power Electronics 2(3): 378-387 (2006) |
| 2005 |
|---|
| 229 | EE | Fei Hu,
Vishwani D. Agrawal:
Dual-transition glitch filtering in probabilistic waveform power estimation.
ACM Great Lakes Symposium on VLSI 2005: 357-360 |
| 228 | EE | Vishwani D. Agrawal,
Alok S. Doshi:
Concurrent Test Generation.
Asian Test Symposium 2005: 294-299 |
| 227 | EE | Raja K. K. R. Sandireddy,
Vishwani D. Agrawal:
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits.
DATE 2005: 1014-1019 |
| 226 | EE | Fei Hu,
Vishwani D. Agrawal:
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis.
ICCD 2005: 366-372 |
| 225 | EE | Yuanlin Lu,
Vishwani D. Agrawal:
Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing.
PATMOS 2005: 217-226 |
| 224 | EE | Tezaswi Raja,
Vishwani D. Agrawal,
Michael L. Bushnell:
Design of Variable Input Delay Gates for Low Dynamic Power Circuits.
PATMOS 2005: 436-445 |
| 223 | EE | Tezaswi Raja,
Vishwani D. Agrawal,
Michael L. Bushnell:
Variable Input Delay CMOS Logic for Low Power Design.
VLSI Design 2005: 598-605 |
| 222 | EE | Kunal K. Dave,
Vishwani D. Agrawal,
Michael L. Bushnell:
Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies.
VLSI Design 2005: 723-729 |
| 221 | EE | Yong Chang Kim,
Vishwani D. Agrawal,
Kewal K. Saluja:
Combinational automatic test pattern generation for acyclic sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 948-956 (2005) |
| 220 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 21(1): 5 (2005) |
| 219 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 21(2): 111 (2005) |
| 218 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 21(3): 199 (2005) |
| 217 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 21(5): 459 (2005) |
| 216 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 21(6): 567 (2005) |
| 2004 |
|---|
| 215 | EE | Junwu Zhang,
Michael L. Bushnell,
Vishwani D. Agrawal:
On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits.
ITC 2004: 617-626 |
| 214 | EE | Tezaswi Raja,
Vishwani D. Agrawal,
Michael L. Bushnell:
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed.
VLSI Design 2004: 1035-1040 |
| 213 | EE | Tezaswi Raja,
Vishwani D. Agrawal,
Michael L. Bushnell:
A Tuturial on the Emerging Nanotechnology Devices.
VLSI Design 2004: 343-360 |
| 212 | EE | Vishwani D. Agrawal:
1985 to 1987: My years with D&T.
IEEE Design & Test of Computers 21(3): 173-174 (2004) |
| 211 | EE | Subhashis Majumder,
Bhargab B. Bhattacharya,
Vishwani D. Agrawal,
Michael L. Bushnell:
A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults.
J. Comput. Sci. Technol. 19(6): 955-964 (2004) |
| 210 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 20(1): 5-6 (2004) |
| 209 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 20(2): 127 (2004) |
| 208 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 20(3): 219 (2004) |
| 207 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 20(4): 327 (2004) |
| 206 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 20(5): 459 (2004) |
| 205 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 20(6): 571 (2004) |
| 2003 |
|---|
| 204 | EE | Vishwani D. Agrawal,
A. V. S. S. Prasad,
Madhusudan V. Atre:
Fault Collapsing via Functional Dominance.
ITC 2003: 274-280 |
| 203 | EE | Vishwani D. Agrawal,
Dong Hyun Baik,
Yong Chang Kim,
Kewal K. Saluja:
Exclusive Test and its Applications to Fault Diagnosis.
VLSI Design 2003: 143-148 |
| 202 | EE | Vishal J. Mehta,
Kunal K. Dave,
Vishwani D. Agrawal,
Michael L. Bushnell:
A Fault-Independent Transitive Closure Algorithm for Redundancy Identification.
VLSI Design 2003: 149-154 |
| 201 | EE | Lan Rao,
Michael L. Bushnell,
Vishwani D. Agrawal:
New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss.
VLSI Design 2003: 353-360 |
| 200 | EE | Tezaswi Raja,
Vishwani D. Agrawal,
Michael L. Bushnell:
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program.
VLSI Design 2003: 527-532 |
| 199 | EE | Pradip A. Thaker,
Vishwani D. Agrawal,
Mona E. Zaghloul:
A test evaluation technique for VLSI circuits using register-transfer level fault modeling.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1104-1113 (2003) |
| 198 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 19(1): 5 (2003) |
| 197 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 19(2): 95 (2003) |
| 196 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 19(3): 219 (2003) |
| 195 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 19(4): 363 (2003) |
| 194 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 19(6): 607 (2003) |
| 2002 |
|---|
| 193 | EE | Vivek Gaur,
Vishwani D. Agrawal,
Michael L. Bushnell:
A New Transitive Closure Algorithm with Application to Redundancy Identification.
DELTA 2002: 496-500 |
| 192 | EE | Aditya D. Sathe,
Michael L. Bushnell,
Vishwani D. Agrawal:
Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects.
ITC 2002: 375-383 |
| 191 | EE | A. V. S. S. Prasad,
Vishwani D. Agrawal,
Madhusudan V. Atre:
A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets.
ITC 2002: 391-397 |
| 190 | EE | Vishwani D. Agrawal,
Michael L. Bushnell:
Electronic Testing for SOC Designers (Tutorial Abstract).
VLSI Design 2002: 20 |
| 189 | EE | Yong Chang Kim,
Vishwani D. Agrawal,
Kewal K. Saluja:
Multiple Faults: Modeling, Simulation and Test.
VLSI Design 2002: 592-597 |
| 188 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 18(1): 5 (2002) |
| 187 | EE | Ashish Giani,
Shuo Sheng,
Michael S. Hsiao,
Vishwani D. Agrawal:
State and Fault Information for Compaction-Based Test Generation.
J. Electronic Testing 18(1): 63-72 (2002) |
| 186 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 18(2): 103-104 (2002) |
| 185 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 18(3): 255 (2002) |
| 184 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 18(4-5): 359 (2002) |
| 183 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 18(6): 567-568 (2002) |
| 2001 |
|---|
| 182 | EE | Ashish Giani,
Shuo Sheng,
Michael S. Hsiao,
Vishwani D. Agrawal:
Efficient spectral techniques for sequential ATPG.
DATE 2001: 204-208 |
| 181 | | Yong Chang Kim,
Vishwani D. Agrawal,
Kewal K. Saluja:
Combinational test generation for various classes of acyclic sequential circuits.
ITC 2001: 1078-1087 |
| 180 | EE | Yong Chang Kim,
Kewal K. Saluja,
Vishwani D. Agrawal:
Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model.
VLSI Design 2001: 143-148 |
| 179 | EE | Ashish Giani,
Shuo Sheng,
Michael S. Hsiao,
Vishwani D. Agrawal:
Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment.
VTS 2001: 163-168 |
| 178 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 17(2): 79 (2001) |
| 177 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 17(3-4): 203 (2001) |
| 176 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 17(5): 367 (2001) |
| 175 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 17(6): 455 (2001) |
| 2000 |
|---|
| 174 | EE | Huan-Chih Tsai,
Kwang-Ting Cheng,
Vishwani D. Agrawal:
A testability metric for path delay faults and its application.
ASP-DAC 2000: 593-598 |
| 173 | EE | Ashish Giani,
Shuo Sheng,
Michael S. Hsiao,
Vishwani D. Agrawal:
Compaction-based test generation using state and fault information.
Asian Test Symposium 2000: 159-164 |
| 172 | EE | Kwang-Ting Cheng,
Vishwani D. Agrawal,
Jing-Yang Jou,
Li-C. Wang,
Chi-Feng Wu,
Shianling Wu:
Collaboration between Industry and Academia in Test Research.
Asian Test Symposium 2000: 17- |
| 171 | EE | Vishwani D. Agrawal,
Kwang-Ting Cheng:
Testing in the Fourth Dimension.
Asian Test Symposium 2000: 2- |
| 170 | EE | José T. de Sousa,
Vishwani D. Agrawal:
Reducing the Complexity of Defect Level Modeling Using the Clustering Effect.
DATE 2000: 640-644 |
| 169 | | Pradip A. Thaker,
Vishwani D. Agrawal,
Mona E. Zaghloul:
Register-transfer level fault modeling and test evaluation techniques for VLSI circuits.
ITC 2000: 940-949 |
| 168 | EE | Vishwani D. Agrawal:
Choice of Tests for Logic Verification and Equivalence Checking.
VLSI Design 2000: 306-311 |
| 167 | EE | Tapan J. Chakraborty,
Vishwani D. Agrawal,
Michael L. Bushnell:
Path delay fault simulation of sequential circuits.
IEEE Trans. VLSI Syst. 8(2): 223-228 (2000) |
| 166 | EE | Tapan J. Chakraborty,
Vishwani D. Agrawal,
Michael L. Bushnell:
Improving path delay testability of sequential circuits.
IEEE Trans. VLSI Syst. 8(6): 736-741 (2000) |
| 165 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 16(1-2): 5 (2000) |
| 164 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 16(3): 163 (2000) |
| 163 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 16(4): 315 (2000) |
| 162 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 16(5): 403-404 (2000) |
| 161 | EE | Marwan A. Gharaybeh,
Vishwani D. Agrawal,
Michael L. Bushnell,
Carlos G. Parodi:
False-Path Removal Using Delay Fault Simulation.
J. Electronic Testing 16(5): 463-476 (2000) |
| 160 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 16(6): 571 (2000) |
| 1999 |
|---|
| 159 | EE | Yong Chang Kim,
Kewal K. Saluja,
Vishwani D. Agrawal:
A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability.
Great Lakes Symposium on VLSI 1999: 300- |
| 158 | | Vishwani D. Agrawal:
Panel: Increasing test coverage in a VLSI desgin course.
ITC 1999: 1131 |
| 157 | EE | Vishwani D. Agrawal,
Michael L. Bushnell,
Ganapathy Parthasarathy,
Rajesh Ramadoss:
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method.
VLSI Design 1999: 434-439 |
| 156 | EE | Keerthi Heragu,
Janak H. Patel,
Vishwani D. Agrawal:
A Test Generator for Segment Delay Faults.
VLSI Design 1999: 484-491 |
| 155 | EE | Subhashis Majumder,
Bhargab B. Bhattacharya,
Vishwani D. Agrawal,
Michael L. Bushnell:
A Complete Characterization of Path Delay Faults through Stuck-at Faults.
VLSI Design 1999: 492-497 |
| 154 | EE | Pradip A. Thaker,
Vishwani D. Agrawal,
Mona E. Zaghloul:
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test.
VTS 1999: 182-188 |
| 153 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 14(1-2): 7 (1999) |
| 152 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 14(3): 187-188 (1999) |
| 151 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 15(1-2): 5 (1999) |
| 150 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 15(3): 215 (1999) |
| 1998 |
|---|
| 149 | EE | Marwan A. Gharaybeh,
Vishwani D. Agrawal,
Michael L. Bushnell:
False-Path Removal Using Delay Fault Simulation.
Asian Test Symposium 1998: 82-87 |
| 148 | EE | Vishwani D. Agrawal,
Sharad C. Seth:
Mutually Disjoint Signals and Probability Calculation in Digital Circuits.
Great Lakes Symposium on VLSI 1998: 307-312 |
| 147 | EE | Carlos G. Parodi,
Vishwani D. Agrawal,
Michael L. Bushnell,
Shianling Wu:
A non-enumerative path delay fault simulator for sequential circuits.
ITC 1998: 934-943 |
| 146 | EE | Pramit Chavda,
James Jacob,
Vishwani D. Agrawal:
Optimizing Logic Design Using Boolean Transforms.
VLSI Design 1998: 218-221 |
| 145 | EE | Ananta K. Majhi,
Vishwani D. Agrawal:
Mixed-Signal Test.
VLSI Design 1998: 285-288 |
| 144 | EE | Ananta K. Majhi,
Vishwani D. Agrawal:
Tutorial: Delay Fault Models and Coverage.
VLSI Design 1998: 364-369 |
| 143 | EE | Subhashis Majumder,
Michael L. Bushnell,
Vishwani D. Agrawal:
Path Delay Testing: Variable-Clock Versus Rated-Clock.
VLSI Design 1998: 470-475 |
| 142 | EE | Subhashis Majumder,
Vishwani D. Agrawal,
Michael L. Bushnell:
On Delay-Untestable Paths and Stuck-Fault Redundancy.
VTS 1998: 194-199 |
| 141 | | Soumitra Bose,
Prathima Agrawal,
Vishwani D. Agrawal:
Deriving Logic Systems for Path Delay Test Generation.
IEEE Trans. Computers 47(8): 829-846 (1998) |
| 140 | EE | Marwan A. Gharaybeh,
Michael L. Bushnell,
Vishwani D. Agrawal:
The path-status graph with application to delay fault simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 324-332 (1998) |
| 139 | EE | Marwan A. Gharaybeh,
Michael L. Bushnell,
Vishwani D. Agrawal:
A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 873-876 (1998) |
| 138 | EE | Vishwani D. Agrawal:
Design of mixed-signal systems for testability.
Integration 26(1-2): 141-150 (1998) |
| 137 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 12(1-2): 5 (1998) |
| 136 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 12(3): 167 (1998) |
| 135 | EE | Lakshminarayana Pappu,
Michael L. Bushnell,
Vishwani D. Agrawal,
Mandyam-Komar Srinivas:
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits.
J. Electronic Testing 12(3): 239-254 (1998) |
| 134 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 13(1): 5 (1998) |
| 133 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 13(2): 75 (1998) |
| 132 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 13(3): 219 (1998) |
| 1997 |
|---|
| 131 | EE | Keerthi Heragu,
Janak H. Patel,
Vishwani D. Agrawal:
Fast identification of untestable delay faults using implications.
ICCAD 1997: 642-647 |
| 130 | | Soumitra Bose,
Vishwani D. Agrawal,
Thomas G. Szymanski:
Algorithms for Switch Level Delay Fault Simulation.
ITC 1997: 982-991 |
| 129 | | Tapan J. Chakraborty,
Vishwani D. Agrawal:
Effective Path Selection for Delay Fault Testing of Sequential Circuits.
ITC 1997: 998-1003 |
| 128 | EE | Vishwani D. Agrawal:
Low-Power Design by Hazard Filtering.
VLSI Design 1997: 193-197 |
| 127 | EE | James Jacob,
P. Srinivas Sivakumar,
Vishwani D. Agrawal:
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs.
VLSI Design 1997: 514-515 |
| 126 | EE | Mandyam-Komar Srinivas,
Michael L. Bushnell,
Vishwani D. Agrawal:
Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation.
VLSI Design 1997: 88-94 |
| 125 | EE | Vishwani D. Agrawal,
Robert C. Aitken,
J. Braden,
Joan Figueras,
S. Kumar,
Hans-Joachim Wunderlich,
Yervant Zorian:
Power Dissipation During Testing: Should We Worry About it?
VTS 1997: 456-457 |
| 124 | EE | Richard M. Chou,
Kewal K. Saluja,
Vishwani D. Agrawal:
Scheduling tests for VLSI systems under power constraints.
IEEE Trans. VLSI Syst. 5(2): 175-185 (1997) |
| 123 | EE | Tapan J. Chakraborty,
Vishwani D. Agrawal,
Michael L. Bushnell:
On variable clock methods for path delay testing of sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1237-1249 (1997) |
| 122 | EE | Srimat T. Chakradhar,
Steven G. Rothweiler,
Vishwani D. Agrawal:
Redundancy removal and test generation for circuits with non-Boolean primitives.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1370-1377 (1997) |
| 121 | EE | Keerthi Heragu,
Vishwani D. Agrawal,
Michael L. Bushnell,
Janak H. Patel:
Improving a nonenumerative method to estimate path delay fault coverage.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 759-762 (1997) |
| 120 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 10(1-2): 5 (1997) |
| 119 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 10(3): 171 (1997) |
| 118 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 11(1): 5 (1997) |
| 117 | EE | Marwan A. Gharaybeh,
Michael L. Bushnell,
Vishwani D. Agrawal:
Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests.
J. Electronic Testing 11(1): 55-67 (1997) |
| 116 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 11(2): 107 (1997) |
| 115 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 11(3): 195 (1997) |
| 1996 |
|---|
| 114 | EE | Vishwani D. Agrawal,
Michael L. Bushnell,
Qing Lin:
Redundancy Identification Using Transitive Closure.
Asian Test Symposium 1996: 4-9 |
| 113 | EE | Kent L. Einspahr,
Sharad C. Seth,
Vishwani D. Agrawal:
Improving Circuit Testability by Clock Control.
Great Lakes Symposium on VLSI 1996: 288-293 |
| 112 | EE | Keerthi Heragu,
Janak H. Patel,
Vishwani D. Agrawal:
SIGMA: a simulator for segment delay faults.
ICCAD 1996: 502-508 |
| 111 | | Marwan A. Gharaybeh,
Michael L. Bushnell,
Vishwani D. Agrawal:
An Exact Non-Enumerative Fault Simulator for Path-Delay Faults.
ITC 1996: 276-285 |
| 110 | | Vishwani D. Agrawal,
Ronald D. Blanton,
Maurizio Damiani:
Synthesis of Self-Testing Finite State Machines from High-Level Specifications.
ITC 1996: 757-766 |
| 109 | EE | Lakshminarayana Pappu,
Michael L. Bushnell,
Vishwani D. Agrawal,
Mandyam-Komar Srinivas:
Statistical path delay fault coverage estimation for synchronous sequential circuits.
VLSI Design 1996: 290-295 |
| 108 | EE | Vishwani D. Agrawal,
David Lee:
Characteristic polynomial method for verification and test of combinational circuits.
VLSI Design 1996: 341-342 |
| 107 | EE | Ananta K. Majhi,
James Jacob,
Lalit M. Patnaik,
Vishwani D. Agrawal:
On test coverage of path delay faults.
VLSI Design 1996: 418-421 |
| 106 | EE | Keerthi Heragu,
Janak H. Patel,
Vishwani D. Agrawal:
Improving accuracy in path delay fault coverage estimation.
VLSI Design 1996: 422-425 |
| 105 | EE | Marwan A. Gharaybeh,
Michael L. Bushnell,
Vishwani D. Agrawal:
Parallel concurrent path-delay fault simulation using single-input change patterns.
VLSI Design 1996: 426-431 |
| 104 | EE | Tapan J. Chakraborty,
Vishwani D. Agrawal:
Design for high-speed testability of stuck-at faults.
VLSI Design 1996: 53-56 |
| 103 | EE | Vishwani D. Agrawal:
Science, Technology, and the Indian Society.
VLSI Design 1996: 6-9 |
| 102 | EE | Keerthi Heragu,
Janak H. Patel,
Vishwani D. Agrawal:
Segment delay faults: a new fault model.
VTS 1996: 32-41 |
| 101 | | Vishwani D. Agrawal:
1995 Asian Test Symposium carves a niche.
IEEE Design & Test of Computers 13(2): 3- (1996) |
| 100 | EE | Mandyam-Komar Srinivas,
James Jacob,
Vishwani D. Agrawal:
Functional test generation for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(7): 831-843 (1996) |
| 99 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 8(2): 111 (1996) |
| 98 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 9(1-2): 5 (1996) |
| 1995 |
|---|
| 97 | EE | Vishwani D. Agrawal,
Bernard Courtois,
Fumiyasu Hirose,
Sandip Kundu,
Chung-Len Lee,
Yinghua Min,
P. Pal Chaudhuri:
Panel: New Research Problems in the Emerging Test Technology.
Asian Test Symposium 1995: 189- |
| 96 | EE | Mandyam-Komar Srinivas,
Vishwani D. Agrawal,
Michael L. Bushnell:
Functional test generation for path delay faults.
Asian Test Symposium 1995: 339-345 |
| 95 | EE | Soumitra Bose,
Vishwani D. Agrawal:
Sequential logic path delay test generation by symbolic analysis.
Asian Test Symposium 1995: 353- |
| 94 | EE | James Sienicki,
Michael L. Bushnell,
Prathima Agrawal,
Vishwani D. Agrawal:
An adaptive distributed algorithm for sequential circuit test generation.
EURO-DAC 1995: 236-241 |
| 93 | | Marwan A. Gharaybeh,
Michael L. Bushnell,
Vishwani D. Agrawal:
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests.
ITC 1995: 139-148 |
| 92 | | Vishwani D. Agrawal,
Tapan J. Chakraborty:
High-Performance Circuit Testing with Slow-Speed Testers.
ITC 1995: 302-310 |
| 91 | EE | Ananta K. Majhi,
James Jacob,
Lalit M. Patnaik,
Vishwani D. Agrawal:
An efficient automatic test generation system for path delay faults in combinational circuits.
VLSI Design 1995: 161-165 |
| 90 | EE | Keerthi Heragu,
Vishwani D. Agrawal,
Michael L. Bushnell:
Statistical methods for delay fault coverage analysis.
VLSI Design 1995: 166-170 |
| 89 | EE | James Sienicki,
Michael L. Bushnell,
Prathima Agrawal,
Vishwani D. Agrawal:
An asynchronous algorithm for sequential circuit test generation on a network of workstations.
VLSI Design 1995: 36-41 |
| 88 | EE | Tapan J. Chakraborty,
Vishwani D. Agrawal:
Robust testing for stuck-at faults.
VLSI Design 1995: 42-46 |
| 87 | EE | Mandyam-Komar Srinivas,
James Jacob,
Vishwani D. Agrawal:
Functional test generation for non-scan sequential circuits.
VLSI Design 1995: 47-52 |
| 86 | EE | Tapan J. Chakraborty,
Vishwani D. Agrawal:
Simulation of at-speed tests for stuck-at faults.
VTS 1995: 216-220 |
| 85 | | Debashis Bhattacharya,
Prathima Agrawal,
Vishwani D. Agrawal:
Test Generation for Path Delay Faults Using Binary Decision Diagrams.
IEEE Trans. Computers 44(3): 434-447 (1995) |
| 84 | EE | Suman Kanjilal,
Srimat T. Chakradhar,
Vishwani D. Agrawal:
A partition and resynthesis approach to testable design of large circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(10): 1268-1276 (1995) |
| 83 | EE | Keerthi Heragu,
Vishwani D. Agrawal,
Michael L. Bushnell:
Fault coverage estimation by test vector sampling.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 590-596 (1995) |
| 82 | EE | Srimat T. Chakradhar,
Mahesh A. Iyer,
Vishwani D. Agrawal:
Energy models for delay testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 728-739 (1995) |
| 81 | EE | Suman Kanjilal,
Srimat T. Chakradhar,
Vishwani D. Agrawal:
Test function embedding algorithms with application to interconnected finite state machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1115-1127 (1995) |
| 80 | EE | Vishwani D. Agrawal,
Srimat T. Chakradhar:
Combinational ATPG theorems for identifying untestable faults in sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1155-1160 (1995) |
| 79 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 6(1): 5-6 (1995) |
| 78 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 6(2): 147 (1995) |
| 77 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 6(3): 263 (1995) |
| 76 | EE | Vishwani D. Agrawal:
Editorial - Special issue on partial scan design.
J. Electronic Testing 7(1-2): 5-6 (1995) |
| 75 | EE | Srimat T. Chakradhar,
Arun Balakrishnan,
Vishwani D. Agrawal:
An exact algorithm for selecting partial scan flip-flops.
J. Electronic Testing 7(1-2): 83-93 (1995) |
| 74 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 7(3): 143 (1995) |
| 1994 |
|---|
| 73 | EE | Keerthi Heragu,
Michael L. Bushnell,
Vishwani D. Agrawal:
An Efficient Path Delay Fault Coverage Estimator.
DAC 1994: 516-521 |
| 72 | EE | Srimat T. Chakradhar,
Arun Balakrishnan,
Vishwani D. Agrawal:
An Exact Algorithm for Selecting Partial Scan Flip-Flops.
DAC 1994: 81-86 |
| 71 | | Suman Kanjilal,
Srimat T. Chakradhar,
Vishwani D. Agrawal:
A Test Function Architecture for Interconnected Finite State Machines.
VLSI Design 1994: 113-116 |
| 70 | | Richard M. Chou,
Kewal K. Saluja,
Vishwani D. Agrawal:
Power Constraint Scheduling of Tests.
VLSI Design 1994: 271-274 |
| 69 | | P. R. Suresh Kumar,
James Jacob,
Mandyam-Komar Srinivas,
Vishwani D. Agrawal:
An Improved Deductive Fault Simulator.
VLSI Design 1994: 307-310 |
| 68 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 5(1): 5 (1994) |
| 67 | EE | Srimat T. Chakradhar,
Vishwani D. Agrawal,
Michael L. Bushnell:
Energy minimization and design for testability.
J. Electronic Testing 5(1): 57-66 (1994) |
| 66 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 5(2-3): 127 (1994) |
| 65 | EE | Vishwani D. Agrawal:
A tale of two designs: the cheapest and the most economic.
J. Electronic Testing 5(2-3): 131-135 (1994) |
| 64 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 5(4): 317 (1994) |
| 1993 |
|---|
| 63 | EE | Prathima Agrawal,
Vishwani D. Agrawal,
Joan Villoldo:
Sequential Circuit Test Generation on a Distributed System.
DAC 1993: 107-111 |
| 62 | EE | Tapan J. Chakraborty,
Vishwani D. Agrawal,
Michael L. Bushnell:
Design for Testability for Path Delay faults in Sequential Circuits.
DAC 1993: 453-457 |
| 61 | | Prathima Agrawal,
Vishwani D. Agrawal,
Joan Villoldo:
Test Pattern Generation for Sequential Circuits on a Network of Workstations.
HPDC 1993: 114-120 |
| 60 | | Soumitra Bose,
Prathima Agrawal,
Vishwani D. Agrawal:
Generation of Compact Delay Tests by Multiple-Path Activation.
ITC 1993: 714-723 |
| 59 | | Suman Kanjilal,
Srimat T. Chakradhar,
Vishwani D. Agrawal:
A Synthesis Approach to Design for Testability.
ITC 1993: 754-763 |
| 58 | | Soumitra Bose,
Prathima Agrawal,
Vishwani D. Agrawal:
A Path Delay Fault Simulator for Sequential Circuits.
VLSI Design 1993: 269-274 |
| 57 | EE | Prathima Agrawal,
Vishwani D. Agrawal,
Sharad C. Seth:
Generating Tests for Delay Faults in Nonscan Circuits.
IEEE Design & Test of Computers 10(1): 20-28 (1993) |
| 56 | EE | Vishwani D. Agrawal,
Charles R. Kime,
Kewal K. Saluja:
A Tutorial on Built-in Self-Test. I. Principles.
IEEE Design & Test of Computers 10(1): 73-82 (1993) |
| 55 | EE | Vishwani D. Agrawal,
Charles R. Kime,
Kewal K. Saluja:
A Tutorial on Built-In Self-Test, Part 2: Applications.
IEEE Design & Test of Computers 10(2): 69-77 (1993) |
| 54 | EE | Soumitra Bose,
Prathima Agrawal,
Vishwani D. Agrawal:
Path delay fault simulation of sequential circuits.
IEEE Trans. VLSI Syst. 1(4): 453-461 (1993) |
| 53 | EE | D. Das,
Sharad C. Seth,
Vishwani D. Agrawal:
Accurate computation of field reject ratio based on fault latency.
IEEE Trans. VLSI Syst. 1(4): 537-545 (1993) |
| 52 | EE | Srimat T. Chakradhar,
Vishwani D. Agrawal,
Steven G. Rothweiler:
A transitive closure algorithm for test generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1015-1028 (1993) |
| 51 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 4(1): 5 (1993) |
| 50 | EE | Srimat T. Chakradhar,
Suman Kanjilal,
Vishwani D. Agrawal:
Finite state machine synthesis with fault tolerant test function.
J. Electronic Testing 4(1): 57-69 (1993) |
| 49 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 4(2): 123 (1993) |
| 48 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 4(3): 199 (1993) |
| 47 | EE | Soumitra Bose,
Prathima Agrawal,
Vishwani D. Agrawal:
The optimistic update theorem for path delay testing in sequential circuits.
J. Electronic Testing 4(3): 285-290 (1993) |
| 46 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 4(4): 295 (1993) |
| 1992 |
|---|
| 45 | EE | Debashis Bhattacharya,
Prathima Agrawal,
Vishwani D. Agrawal:
Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions.
DAC 1992: 159-164 |
| 44 | EE | Tapan J. Chakraborty,
Vishwani D. Agrawal,
Michael L. Bushnell:
Delay Fault Models and Test Generation for Random Logic Sequential Circuits.
DAC 1992: 165-172 |
| 43 | EE | Srimat T. Chakradhar,
Suman Kanjilal,
Vishwani D. Agrawal:
Finite State Machine Synthesis with Fault Tolerant Test Function.
DAC 1992: 562-567 |
| 42 | | Mandyam-Komar Srinivas,
James Jacob,
Vishwani D. Agrawal:
Finite State Machine Testing Based on Growth and Dissappearance Faults.
FTCS 1992: 238-245 |
| 41 | | Kwang-Ting Cheng,
Vishwani D. Agrawal:
Initializability Consideration in Sequential Machine Synthesis.
IEEE Trans. Computers 41(3): 374-379 (1992) |
| 40 | EE | Vishwani D. Agrawal,
Srimat T. Chakradhar:
Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems.
IEEE Trans. Parallel Distrib. Syst. 3(6): 739-746 (1992) |
| 39 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 3(2): 105 (1992) |
| 38 | EE | Ernst Ulrich,
Karen Lentz,
Jack H. Arabian,
Michael Gustin,
Vishwani D. Agrawal,
Pier Luca Montessoro:
The Comparative and Concurrent Simulation of discrete-event experiments.
J. Electronic Testing 3(2): 107-118 (1992) |
| 37 | EE | James Jacob,
Vishwani D. Agrawal:
Multiple fault detection in two-level multi-output circuits.
J. Electronic Testing 3(2): 171-173 (1992) |
| 1991 |
|---|
| 36 | EE | Srimat T. Chakradhar,
Vishwani D. Agrawal:
A Transitive Closure Based Algorithm for Test Generation.
DAC 1991: 353-358 |
| 35 | | Vishwani D. Agrawal:
Design and Test-The Two Sides of a Coin.
ICCD 1991: 12 |
| 34 | | Joan Villoldo,
Prathima Agrawal,
Vishwani D. Agrawal:
Stafan Algorithms for MOS Circuits.
ICCD 1991: 56-59 |
| 33 | | Dharam Vir Das,
Sharad C. Seth,
Vishwani D. Agrawal:
Estimating the Quality of Manufactured Digital Sequential Circuits.
ITC 1991: 210-217 |
| 1990 |
|---|
| 32 | EE | Vishwani D. Agrawal,
Kwang-Ting Cheng:
Test Function Specification in Synthesis.
DAC 1990: 235-240 |
| 31 | EE | Kwang-Ting Cheng,
Vishwani D. Agrawal:
An Entropy Measure for the Complexity of Multi-Output Boolean Functions.
DAC 1990: 302-305 |
| 30 | EE | Srimat T. Chakradhar,
Vishwani D. Agrawal,
Michael L. Bushnell:
Automatic Test Generation Using Quadratic 0-1 Programming.
DAC 1990: 654-659 |
| 29 | EE | Vishwani D. Agrawal,
Kwang-Ting Cheng:
An architecture for synthesis of testable finite state machines.
EURO-DAC 1990: 612-616 |
| 28 | | Vishwani D. Agrawal,
Srimat T. Chakradhar:
Logic Simulation and Parallel Processing.
ICCAD 1990: 496-499 |
| 27 | EE | Vishwani D. Agrawal,
Srimat T. Chakradhar:
Performance estimation in a massively parallel system.
SC 1990: 306-313 |
| 26 | EE | Vishwani D. Agrawal,
Hatsuyoshi Kato:
Fault Sampling Revisited.
IEEE Design & Test of Computers 7(4): 32-35 (1990) |
| 25 | EE | Srimat T. Chakradhar,
Vishwani D. Agrawal,
Michael L. Bushnell,
Thomas K. Truong:
Neural Net and Boolean Satisfiability Models of Logic Circuits.
IEEE Design & Test of Computers 7(5): 54-57 (1990) |
| 24 | | Kwang-Ting Cheng,
Vishwani D. Agrawal,
Ernest S. Kuh:
A Simulation-Based Method for Generating Tests for Sequential Circuits.
IEEE Trans. Computers 39(12): 1456-1463 (1990) |
| 23 | | Kwang-Ting Cheng,
Vishwani D. Agrawal:
A Partial Scan Method for Sequential Circuits with Feedback.
IEEE Trans. Computers 39(4): 544-549 (1990) |
| 22 | | Sharad C. Seth,
Vishwani D. Agrawal,
Hassan Farhat:
A Statistical Theory of Digital Circuit Testability.
IEEE Trans. Computers 39(4): 582-586 (1990) |
| 21 | EE | Srimat T. Chakradhar,
Michael L. Bushnell,
Vishwani D. Agrawal:
Toward massively parallel automatic test generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(9): 981-994 (1990) |
| 20 | EE | Vishwani D. Agrawal:
Editorial.
J. Electronic Testing 1(2): 101 (1990) |
| 19 | EE | Vishwani D. Agrawal,
Kwang-Ting Cheng:
Finite state machine synthesis with embedded test function.
J. Electronic Testing 1(3): 221-228 (1990) |
| 1989 |
|---|
| 18 | | Prathima Agrawal,
Vishwani D. Agrawal,
Kwang-Ting Cheng,
R. Tutundjian:
Fault Simulation in a Pipelined Multiprocessor System.
ITC 1989: 727-734 |
| 17 | EE | Vishwani D. Agrawal,
Kwang-Ting Cheng,
Prathima Agrawal:
A directed search method for test generation using a concurrent simulator.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(2): 131-138 (1989) |
| 1988 |
|---|
| 16 | EE | Vishwani D. Agrawal,
Kwang-Ting Cheng,
Prathima Agrawal:
Contest: A Concurrent Test Generator for Sequential Circuits.
DAC 1988: 84-89 |
| 1986 |
|---|
| 15 | | Vishwani D. Agrawal,
M. Ray Mercer:
Deterministic Versus Random Testing.
ITC 1986: 718 |
| 1985 |
|---|
| 14 | EE | Vishwani D. Agrawal,
Samuel H. C. Poon:
VLSI design process.
ACM Conference on Computer Science 1985: 74-78 |
| 13 | EE | Prathima Agrawal,
Vishwani D. Agrawal,
Nripendra N. Biswas:
Multiple output minimization.
DAC 1985: 674-680 |
| 12 | | Vishwani D. Agrawal:
STAFAN Takes a Middle Course.
ITC 1985: 796 |
| 11 | | Sunil K. Jain,
Vishwani D. Agrawal:
Modeling and Test Generation Algorithms for MOS Circuits.
IEEE Trans. Computers 34(5): 426-433 (1985) |
| 1984 |
|---|
| 10 | | Vishwani D. Agrawal:
Will Testability Analysis Replace Fault Simulation ?
ITC 1984: 718-718 |
| 9 | EE | Sharad C. Seth,
Vishwani D. Agrawal:
Characterizing the LSI Yield Equation from Wafer Test Data.
IEEE Trans. on CAD of Integrated Circuits and Systems 3(2): 123-126 (1984) |
| 1982 |
|---|
| 8 | | Vishwani D. Agrawal,
M. Ray Mercer:
Testability Measures : What Do They Tell Us ?
ITC 1982: 391-399 |
| 1981 |
|---|
| 7 | | M. Ray Mercer,
Vishwani D. Agrawal,
Carlos M. Roman:
Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation.
ITC 1981: 561-565 |
| 6 | | Vishwani D. Agrawal:
An Information Theoretic Approach to Digital Fault Testing.
IEEE Trans. Computers 30(8): 582-587 (1981) |
| 1979 |
|---|
| 5 | | Vishwani D. Agrawal:
Author's Reply.
IEEE Trans. Computers 28(8): 581 (1979) |
| 4 | | Vishwani D. Agrawal:
Comments on ``An Approach to Highly Integrated Computer-Maintained Cellular Arrays''.
IEEE Trans. Computers 28(9): 691-693 (1979) |
| 1978 |
|---|
| 3 | | Vishwani D. Agrawal:
When to Use Random Testing.
IEEE Trans. Computers 27(11): 1054-1055 (1978) |
| 1976 |
|---|
| 2 | | Prathima Agrawal,
Vishwani D. Agrawal:
On Monte Carlo Testing of Logic Tree Networks.
IEEE Trans. Computers 25(6): 664-667 (1976) |
| 1975 |
|---|
| 1 | | Prathima Agrawal,
Vishwani D. Agrawal:
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks.
IEEE Trans. Computers 24(7): 691-695 (1975) |
