2008 |
24 | EE | Saurabh Jain,
W. Robert Daasch,
David Armbrust:
Analyzing the Impact of Fault Tolerant BIST for VLSI Design.
DFT 2008: 152-160 |
2006 |
23 | EE | Ritesh P. Turakhia,
W. Robert Daasch,
Joel Lurkins,
Brady Benware:
Changing Test and Data Modeling Requirements for Screening Latent Defects as Statistical Outliers.
IEEE Design & Test of Computers 23(2): 100-109 (2006) |
2005 |
22 | EE | Ritesh P. Turakhia,
Brady Benware,
Robert Madge,
Thaddeus T. Shannon,
W. Robert Daasch:
Defect Screening Using Independent Component Analysis on I_DDQ.
VTS 2005: 427-432 |
2004 |
21 | | Haiqiao Xiao,
Rolf Schaumann,
W. Robert Daasch,
Phillip K. Wong,
Branimir Pejcinovic:
A radio-frequency CMOS active inductor and its application in designing high-Q filters.
ISCAS (4) 2004: 197-200 |
20 | EE | W. Robert Daasch,
Manu Rehani:
Dude! Where's my data? - Cracking Open the Hermetically Sealed Tester.
ITC 2004: 1428 |
19 | EE | Robert Madge,
Brady Benware,
Ritesh P. Turakhia,
W. Robert Daasch,
Chris Schuermyer,
Jens Ruffler:
In Search of the Optimum Test Set - Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost.
ITC 2004: 203-212 |
18 | EE | Chris Schuermyer,
Jens Ruffler,
W. Robert Daasch:
Minimum Testing Requirements to Screen Temperature Dependent Defects.
ITC 2004: 300-308 |
17 | EE | Ethan Long,
W. Robert Daasch,
Robert Madge,
Brady Benware:
Detection of Temperature Sensitive Defects Using ZTC.
VTS 2004: 185-192 |
2003 |
16 | EE | Chris Schuermyer,
Brady Benware,
Kevin Cota,
Robert Madge,
W. Robert Daasch,
L. Ning:
Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ.
ITC 2003: 565-573 |
15 | EE | Brady Benware,
Robert Madge,
Cam Lu,
W. Robert Daasch:
Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs.
VTS 2003: 39-46 |
14 | EE | Robert Madge,
Brady Benware,
W. Robert Daasch:
Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs.
IEEE Design & Test of Computers 20(5): 46-53 (2003) |
2002 |
13 | EE | Chee How Lim,
W. Robert Daasch,
George Cai:
A Thermal-Aware Superscalar Microprocessor (invited).
ISQED 2002: 517-522 |
12 | EE | W. Robert Daasch,
Kevin Cota,
James McNames,
Robert Madge:
Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data.
ITC 2002: 1240 |
11 | EE | David Turner,
David Abercrombie,
James McNames,
W. Robert Daasch,
Robert Madge:
Isolating and Removing Sources of Variation in Test Data.
ITC 2002: 464-471 |
10 | EE | Robert Madge,
B. H. Goh,
V. Rajagopalan,
C. Macchietto,
W. Robert Daasch,
Chris Schuermyer,
C. Taylor,
David Turner:
Screening MinVDD Outliers Using Feed-Forward Voltage Testing.
ITC 2002: 673-682 |
9 | EE | Robert Madge,
Manu Rehani,
Kevin Cota,
W. Robert Daasch:
Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies.
VTS 2002: 69-74 |
8 | EE | Ali Keshavarzi,
James Tschanz,
Siva Narendra,
Vivek De,
W. Robert Daasch,
Kaushik Roy,
Manoj Sachdev,
Charles F. Hawkins:
Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits.
IEEE Design & Test of Computers 19(5): 36-43 (2002) |
7 | EE | W. Robert Daasch,
James McNames,
Robert Madge,
Kevin Cota:
Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort.
IEEE Design & Test of Computers 19(5): 74-81 (2002) |
2001 |
6 | | W. Robert Daasch,
Kevin Cota,
James McNames,
Robert Madge:
Neighbor selection for variance reduction in I_DDQ and other parametric data.
ITC 2001: 92-100 |
2000 |
5 | | W. Robert Daasch,
James McNames,
Daniel Bockelman,
Kevin Cota:
Variance reduction using wafer patterns in I_ddQ data.
ITC 2000: 189-198 |
4 | EE | Ashutosh S. Dhodapkar,
Chee How Lim,
George Cai,
W. Robert Daasch:
TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator.
PACS 2000: 112-125 |
1995 |
3 | | Michael A. Driscoll,
W. Robert Daasch:
Accurate Predictions of Parallel Program Execution Time.
J. Parallel Distrib. Comput. 25(1): 16-30 (1995) |
1993 |
2 | | Pan Wu,
Rolf Schaumann,
W. Robert Daasch:
A 20 MHz Fully-balanced Transconductance-C Filter in 2 µm CMOS Technology.
ISCAS 1993: 1188-1191 |
1987 |
1 | | William A. Payne III,
Fillia Makedon,
W. Robert Daasch:
High Speed Interconnection Using the Clos Network.
ICS 1987: 96-111 |