Jean Michel Portal

2008
30	EE	Manuel Sellier, Jean Michel Portal, Bertrand Borot, Steve Colquhoun, Richard Ferrant, Frédéric Boeuf, Alexis Farcy: Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. ISQED 2008: 492-497
29	EE	Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean Michel Portal: Metal filling impact on standard cells: definition of the metal fill corner concept. SBCCI 2008: 16-21
2007
28	EE	Laurent Lopez, Jean Michel Portal, Didier Née: A New Embedded Measurement Structure for eDRAM Capacitor CoRR abs/0710.4736: (2007)
2006
27	EE	B. Saillet, A. Regnier, Jean Michel Portal, B. Delsuc, R. Laffont, Pascal Masson, Rachid Bouchakour: MM11 based flash memory cell model including characterization procedure. ISCAS 2006
2005
26	EE	Laurent Lopez, Jean Michel Portal, Didier Née: A New Embedded Measurement Structure for eDRAM Capacitor. DATE 2005: 462-463
25	EE	B. Saillet, Jean Michel Portal, Didier Née: Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring. DFT 2005: 131-139
24	EE	Jean Michel Portal, H. Aziza, Didier Née: EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement. J. Electronic Testing 21(1): 33-42 (2005)
2004
23	EE	S. Bernardini, Jean Michel Portal, Pascal Masson: A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology. DATE 2004: 1404-1405
22		Anna Labbé, Annie Pérez, Jean Michel Portal: Efficient hardware implementation of a CRYPTO-MEMORY based on AES algorithm and SRAM architecture. ISCAS (2) 2004: 637-640
2003
21	EE	L. Forli, Jean Michel Portal, Didier Née, Bertrand Borot: Infrastructure IP for Back-End Yield Improvement. ITC 2003: 1129-1134
20	EE	Jean Michel Portal, H. Aziza, Didier Née: EEPROM Memory: Threshold Voltage Built In Self Diagnosis. ITC 2003: 23-28
2002
19	EE	Jean Michel Portal, L. Forli, Didier Née: Floating-gate EEPROM cell: threshold voltage sensibility to geometry. ISCAS (1) 2002: 557-560
18	EE	Jean Michel Portal, L. Forli, Didier Née: Floating-gate EEPROM cell model based on MOS model 9. ISCAS (3) 2002: 799-802
17	EE	Jean Michel Portal, L. Forli, H. Aziza, Didier Née: An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell. ITC 2002: 31-36
16	EE	Jean Michel Portal, L. Forli, H. Aziza, Didier Née: An Automated Design Methodology for EEPROM Cell (ADE). MTDT 2002: 137-142
2001
15		Michel Renovell, Penelope Faure, Jean Michel Portal, Joan Figueras, Yervant Zorian: IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC 2001: 924-931
14	EE	Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian: A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electronic Testing 17(3-4): 283-290 (2001)
2000
13	EE	Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian: TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium 2000: 323-328
12	EE	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electronic Testing 16(3): 289-299 (2000)
11	EE	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electronic Testing 16(5): 513-520 (2000)
1999
10	EE	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium 1999: 363-368
9	EE	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE 1999: 618-622
8	EE	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electronic Testing 14(1-2): 159-167 (1999)
1998
7	EE	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium 1998: 266-271
6	EE	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE 1998: 82-88
5	EE	Cecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi: Novel Technique for Testing FPGAs. DATE 1998: 89-
4	EE	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL 1998: 139-148
3	EE	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-based FPGA's: testing the LUT/RAM modules. ITC 1998: 1102-1111
2	EE	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Interconnect of RAM-Based FPGAs. IEEE Design & Test of Computers 15(1): 45-50 (1998)
1997
1	EE	Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium 1997: 254-

Coauthor Index

1	H. Aziza	[16] [17] [20] [24]
2	S. Bernardini	[23]
3	Frédéric Boeuf	[30]
4	Bertrand Borot	[21] [30]
5	Rachid Bouchakour	[27]
6	Philippe Coll	[29]
7	Steve Colquhoun	[30]
8	B. Delsuc	[27]
9	Alexis Farcy	[30]
10	Penelope Faure	[13] [14] [15]
11	Richard Ferrant	[30]
12	Joan Figueras	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
13	L. Forli	[16] [17] [18] [19] [21]
14	Anna Labbé	[22]
15	R. Laffont	[27]
16	Laurent Lopez	[26] [28]
17	Pascal Masson	[23] [27]
18	Cecilia Metra	[5]
19	Philippe Mico	[29]
20	G. Mojoli	[5]
21	Didier Née	[16] [17] [18] [19] [20] [21] [24] [25] [26] [28]
22	Sandro Pastore	[5]
23	Annie Pérez	[22]
24	Fabrice Picot	[29]
25	A. Regnier	[27]
26	Laurent Remy	[29]
27	Michel Renovell	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
28	B. Saillet	[25] [27]
29	Davide Salvi	[5]
30	Giacomo R. Sechi	[5]
31	Manuel Sellier	[30]
32	Yervant Zorian	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]

Colors in the list of coauthors