| 2003 |
|---|
| 13 | EE | Mahesh A. Iyer:
Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation.
ITC 2003: 299-308 |
| 12 | EE | Mahesh A. Iyer:
A Robust and Scalable Technique for the Constraints Solving Problem in High-Level Verification.
MTV 2003: 95- |
| 2000 |
|---|
| 11 | EE | David E. Long,
Mahesh A. Iyer,
Miron Abramovici:
FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults.
ACM Trans. Design Autom. Electr. Syst. 5(3): 631-657 (2000) |
| 1999 |
|---|
| 10 | EE | Leon Stok,
Andrew J. Sullivan,
Mahesh A. Iyer:
Wavefront Technology Mapping.
DATE 1999: 531- |
| 9 | EE | Narendra V. Shenoy,
Mahesh A. Iyer,
Robert F. Damiano,
Kevin Harer,
Hi-Keung Tony Ma,
Paul Thilking:
A Robust Solution to the Timing Convergence Problem in High-Performance Design.
ICCD 1999: 250-257 |
| 8 | | Mahesh A. Iyer:
High Time For High Level ATPG.
ITC 1999: 1112 |
| 1996 |
|---|
| 7 | EE | Mahesh A. Iyer,
David E. Long,
Miron Abramovici:
Identifying Sequential Redundancies Without Search.
DAC 1996: 457-462 |
| 6 | EE | Mahesh A. Iyer,
Miron Abramovici:
FIRE: a fault-independent combinational redundancy identification algorithm.
IEEE Trans. VLSI Syst. 4(2): 295-301 (1996) |
| 1995 |
|---|
| 5 | EE | David E. Long,
Mahesh A. Iyer,
Miron Abramovici:
Identifying sequentially untestable faults using illegal states.
VTS 1995: 4-11 |
| 4 | EE | Srimat T. Chakradhar,
Mahesh A. Iyer,
Vishwani D. Agrawal:
Energy models for delay testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 728-739 (1995) |
| 1994 |
|---|
| 3 | | Mahesh A. Iyer,
Miron Abramovici:
Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!").
ITC 1994: 259-266 |
| 2 | | Mahesh A. Iyer,
Miron Abramovici:
Low-Cost Redundancy Identification for Combinatorial Circuits.
VLSI Design 1994: 315-318 |
| 1992 |
|---|
| 1 | | Miron Abramovici,
Mahesh A. Iyer:
One-Pass Redundancy Identification and Removal.
ITC 1992: 807-815 |
