2008 |
39 | EE | Hans G. Kerkhoff,
Jarkko J. M. Huijts:
Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications.
DELTA 2008: 38-44 |
38 | EE | Oscar Kuiken,
Xiao Zhang,
Hans G. Kerkhoff:
Built-in-Self-Diagnostics for a NoC-Based Reconfigurable IC for Dependable Beamforming Applications.
DFT 2008: 45-53 |
2007 |
37 | EE | Hans G. Kerkhoff:
Testing Microelectronic Biofluidic Systems.
IEEE Design & Test of Computers 24(1): 72-82 (2007) |
2006 |
36 | EE | Hans G. Kerkhoff,
X. Zhang,
R. W. Barber,
D. R. Emerson:
Fault Modelling and Co-Simulation in FlowFET-Based Biological Array Systems.
DELTA 2006: 177-182 |
2005 |
35 | EE | Hans G. Kerkhoff:
The test search for true mixed-signal cores.
Microelectronics Journal 36(12): 1103-1111 (2005) |
2004 |
34 | EE | Hans G. Kerkhoff,
Arun A. Joseph:
Testability Issues in Superconductor Electronic.
DELTA 2004: 9-14 |
33 | EE | Octavian Petre,
Hans G. Kerkhoff:
Scan Test Strategy for Asynchronous-Synchronous Interfaces.
J. Electronic Testing 20(6): 639-645 (2004) |
2003 |
32 | EE | Arun A. Joseph,
Hans G. Kerkhoff:
Towards Structural Testing of Superconductor Electronics.
ITC 2003: 1182-1191 |
31 | EE | Hans G. Kerkhoff,
Mustafa Acar:
Testable Design and Testing of Micro-Electro-Fluidic Arrays.
VTS 2003: 403-409 |
30 | EE | Nur Engin,
Hans G. Kerkhoff:
Fast Fault Simulation for Nonlinear Analog Circuits.
IEEE Design & Test of Computers 20(2): 40-47 (2003) |
29 | EE | Frank te Beest,
Ad M. G. Peeters,
Kees van Berkel,
Hans G. Kerkhoff:
Synchronous Full-Scan for Asynchronous Handshake Circuits.
J. Electronic Testing 19(4): 397-406 (2003) |
28 | EE | Hans G. Kerkhoff,
Bozena Kaminska:
Analog and mixed signal test techniques for SoCs.
Microelectronics Journal 34(10): 887-888 (2003) |
27 | EE | M. Stancic,
Hans G. Kerkhoff:
Testability-analysis driven test-generation of analogue cores.
Microelectronics Journal 34(10): 913-917 (2003) |
2002 |
26 | EE | Octavian Petre,
Hans G. Kerkhoff:
On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications.
Asian Test Symposium 2002: 122- |
25 | EE | Hans G. Kerkhoff,
Arun A. Joseph,
Sander Heuvelmans:
Testable Design and Testing of High-Speed Superconductor Microelectronics.
DELTA 2002: 8-12 |
24 | EE | Frank te Beest,
Ad M. G. Peeters,
Marc Verra,
Kees van Berkel,
Hans G. Kerkhoff:
Automatic Scan Insertion and Test Generation for Asynchronous Circuits.
ITC 2002: 804-813 |
23 | EE | M. Stancic,
L. Fang,
M. H. H. Weusthof,
R. M. W. Tijink,
Hans G. Kerkhoff:
A New Test Generation Approach for Embedded Analogue Cores in SoC.
ITC 2002: 861-869 |
22 | EE | Salvador Mir,
H. Bederr,
R. D. (Shawn) Blanton,
Hans G. Kerkhoff,
H. J. Klim:
SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow?
VTS 2002: 449-450 |
21 | EE | V. A. Zivkovic,
Ronald J. W. T. Tangelder,
Hans G. Kerkhoff:
An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures.
J. Electronic Testing 18(2): 203-212 (2002) |
2001 |
20 | EE | Octavian Petre,
Hans G. Kerkhoff:
Increasing the Fault Coverage in Multiple Clock Domain Systems by Using On-Line Testing of Synchronizers.
IOLTW 2001: 95-99 |
19 | | Erik H. Volkerink,
Ajay Khoche,
Linda A. Kamas,
Jochen Rivoir,
Hans G. Kerkhoff:
Tackling test trade-offs from design, manufacturing to market using economic modeling.
ITC 2001: 1098-1107 |
18 | EE | David San Segundo Bello,
Ronald J. W. T. Tangelder,
Hans G. Kerkhoff:
Modeling a Verification Test System for Mixed-Signal Circuits.
IEEE Design & Test of Computers 18(1): 63-71 (2001) |
17 | EE | Hans G. Kerkhoff,
Han Speek,
M. Shashani,
Manoj Sachdev:
Design for Delay Testability in High-Speed Digital ICs.
J. Electronic Testing 17(3-4): 225-231 (2001) |
16 | EE | Hans G. Kerkhoff,
Hans P. A. Hendriks:
Fault Modeling and Fault Simulation in Mixed Micro-Fluidic Microelectronic Systems.
J. Electronic Testing 17(5): 427-437 (2001) |
2000 |
15 | EE | V. A. Zivkovic,
Ronald J. W. T. Tangelder,
Hans G. Kerkhoff:
Design and Test Space Exploration of Transport-Triggered Architectures.
DATE 2000: 146- |
14 | EE | Hans G. Kerkhoff,
Mansour Shashaani,
Manoj Sachdev:
A Low-Speed BIST Framework for High-Performance Circuit Testing.
VTS 2000: 349-358 |
1999 |
13 | EE | Manoj Sachdev,
Hans G. Kerkhoff:
Configurations for IDDQ-Testable PLAs.
IEEE Design & Test of Computers 16(2): 58-65 (1999) |
12 | EE | Chris Feige,
Jan Ten Pierick,
Clemens Wouters,
Ronald J. W. T. Tangelder,
Hans G. Kerkhoff:
Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach.
J. Electronic Testing 14(1-2): 125-131 (1999) |
11 | EE | Richard Rosing,
Hans G. Kerkhoff,
Ronald J. W. T. Tangelder,
Manoj Sachdev:
Off-Chip Diagnosis of Aperture Jitter in Full-Flash Analog-to-Digital Converters.
J. Electronic Testing 14(1-2): 67-74 (1999) |
10 | EE | Nur Engin,
Hans G. Kerkhoff,
Ronald J. W. T. Tangelder,
Han Speek:
Integrated Design and Test of Mixed-Signal Circuits.
J. Electronic Testing 14(1-2): 75-83 (1999) |
1998 |
9 | EE | Hans G. Kerkhoff:
Microsystem Testing: Challenge or Common Knowledge?.
Asian Test Symposium 1998: 510-511 |
1997 |
8 | EE | Ronald J. W. T. Tangelder,
G. Diemel,
Hans G. Kerkhoff:
Smart sensor system application: an integrated compass.
ED&TC 1997: 195-199 |
7 | EE | V. Kaal,
Hans G. Kerkhoff:
Compact structural test generation for analog macros.
ED&TC 1997: 581-587 |
1990 |
6 | | Jon T. Butler,
Hans G. Kerkhoff,
Siep Onneweer:
A Comparative Analysis of Multiplexer Techniques for the Minimization of Function Cost Using the Costtable Approach.
ISMVL 1990: 286-291 |
5 | EE | R. P. van Riessen,
Hans G. Kerkhoff,
A. Kloppenburg:
Designing and Implementing an Architecture with Boundary Scan.
IEEE Design & Test of Computers 7(1): 9-19 (1990) |
4 | EE | Gertjan J. Hemink,
Berend W. Meijer,
Hans G. Kerkhoff:
Testability analysis of analog systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(6): 573-583 (1990) |
1988 |
3 | | Gertjan J. Hemink,
Berend W. Meijer,
Hans G. Kerkhoff:
TASTE: A Tool for Analog System Testability Evaluation.
ITC 1988: 829-838 |
2 | | Jon T. Butler,
Hans G. Kerkhoff:
Multiple-Valued CCD Circuits.
IEEE Computer 21(4): 58-69 (1988) |
1981 |
1 | | Hans G. Kerkhoff,
Marius L. Tervoert:
Multiple-Valued Logic Charge-Coupled Devices.
IEEE Trans. Computers 30(9): 644-652 (1981) |