| |
| 2004 | ||
|---|---|---|
| 3 | EE | Jay J. Nejedlo: Functional Test Coverage Effectiveness on the Decline. ITC 2004: 1424 |
| 2003 | ||
| 2 | EE | Jay J. Nejedlo: TRIBuTETM Board and Platform Test Methodology: Intel's Next-Generation Test and Validation Methodology for Platforms. ITC 2003: 783 |
| 1 | EE | Jay J. Nejedlo: IBISTTM (Interconnect Built-in Self-Test) Architecture and Methodology for PCI Express: Intel?s Next-Generation Test and Validation Methodology for Performance IO. ITC 2003: 784 |