| 2005 |
|---|
| 10 | EE | Tom Waayers,
Erik Jan Marinissen,
Maurice Lousberg:
IEEE Std 1500 Compliant Infrastructure forModular SOC Testing.
Asian Test Symposium 2005: 450 |
| 2004 |
|---|
| 9 | EE | Geert Seuren,
Tom Waayers:
Extending the Digital Core-based Test Methodology to Support Mixed-Signal.
ITC 2004: 281-289 |
| 2003 |
|---|
| 8 | EE | Tom Waayers:
An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips.
ITC 2003: 1145-1154 |
| 7 | EE | Leon van de Logt,
Frank van der Heyden,
Tom Waayers:
An extension to JTAG for at-speed debug on a system.
ITC 2003: 785-792 |
| 6 | EE | Bart Vermeulen,
Tom Waayers,
Sjaak Bakker:
Multi-TAP Controller Architecture for Digital System Chips.
J. Electronic Testing 19(4): 417-424 (2003) |
| 2002 |
|---|
| 5 | EE | Bart Vermeulen,
Tom Waayers,
Sjaak Bakker:
EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips.
ITC 2002: 55-63 |
| 4 | EE | Bart Vermeulen,
Tom Waayers,
Sandeep Kumar Goel:
Core-Based Scan Architecture for Silicon Debug.
ITC 2002: 638-647 |
| 3 | EE | Harald P. E. Vranken,
Tom Waayers,
Hérvé Fleury,
David Lelouvier:
Enhanced Reduced Pin-Count Test for Full-Scan Design.
J. Electronic Testing 18(2): 129-143 (2002) |
| 2001 |
|---|
| 2 | | Harald P. E. Vranken,
Tom Waayers,
Hérvé Fleury,
David Lelouvier:
Enhanced reduced pin-count test for full-scan design.
ITC 2001: 738-747 |
| 1 | EE | Sandeep Koranne,
Tom Waayers,
Robert Beurze,
Clemens Wouters,
Sunil Kumar,
G. S. Visweswara:
A P1500 Compliant Programable BistShell for Embedded Memories.
MTDT 2001: 21-28 |
