Tom Waayers

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10EETom Waayers, Erik Jan Marinissen, Maurice Lousberg: IEEE Std 1500 Compliant Infrastructure forModular SOC Testing. Asian Test Symposium 2005: 450
9EEGeert Seuren, Tom Waayers: Extending the Digital Core-based Test Methodology to Support Mixed-Signal. ITC 2004: 281-289
8EETom Waayers: An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips. ITC 2003: 1145-1154
7EELeon van de Logt, Frank van der Heyden, Tom Waayers: An extension to JTAG for at-speed debug on a system. ITC 2003: 785-792
6EEBart Vermeulen, Tom Waayers, Sjaak Bakker: Multi-TAP Controller Architecture for Digital System Chips. J. Electronic Testing 19(4): 417-424 (2003)
5EEBart Vermeulen, Tom Waayers, Sjaak Bakker: EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. ITC 2002: 55-63
4EEBart Vermeulen, Tom Waayers, Sandeep Kumar Goel: Core-Based Scan Architecture for Silicon Debug. ITC 2002: 638-647
3EEHarald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier: Enhanced Reduced Pin-Count Test for Full-Scan Design. J. Electronic Testing 18(2): 129-143 (2002)
2 Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier: Enhanced reduced pin-count test for full-scan design. ITC 2001: 738-747
1EESandeep Koranne, Tom Waayers, Robert Beurze, Clemens Wouters, Sunil Kumar, G. S. Visweswara: A P1500 Compliant Programable BistShell for Embedded Memories. MTDT 2001: 21-28

Coauthor Index

1Sjaak Bakker [5] [6]
2Robert Beurze [1]
3Hérvé Fleury [2] [3]
4Sandeep Kumar Goel [4]
5Frank van der Heyden [7]
6Sandeep Koranne [1]
7Sunil Kumar [1]
8David Lelouvier [2] [3]
9Leon van de Logt [7]
10Maurice Lousberg [10]
11Erik Jan Marinissen [10]
12Geert Seuren [9]
13Bart Vermeulen [4] [5] [6]
14G. S. Visweswara [1]
15Harald P. E. Vranken [2] [3]
16Clemens Wouters [1]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)