Dilip K. Bhavsar

2005
19	EE	Dilip K. Bhavsar: A Built-in Self-Test Method for Write-only Content Addressable Memories. VTS 2005: 9-14
2003
18	EE	Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies: Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor. ICCD 2003: 180-186
17	EE	Scott Erlanger, Dilip K. Bhavsar, Richard A. Davies: Testability Features of the Alpha 21364 Microprocessor. ITC 2003: 764-772
2002
16	EE	Dilip K. Bhavsar, Richard A. Davies: Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor. VTS 2002: 16-24
2001
15	EE	Dilip K. Bhavsar, Rishan Tan: Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits. VLSI Design 2001: 385-390
14	EE	Dilip K. Bhavsar: Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester. VTS 2001: 94-101
2000
13	EE	Dilip K. Bhavsar: Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability. IEEE Design & Test of Computers 17(2): 94-99 (2000)
1999
12		Dilip K. Bhavsar: An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264. ITC 1999: 311-318
11		Dilip K. Bhavsar: ITC 99 Panels. IEEE Design & Test of Computers 16(4): 96-99 (1999)
1998
10	EE	Dilip K. Bhavsar, David R. Akeson, Michael K. Gowan, Daniel B. Jackson: Testability access of the high speed test features in the Alpha 21264 microprocessor. ITC 1998: 487-
9	EE	Dilip K. Bhavsar, Ugonna Echeruo, David R. Akeson, William J. Bowhill: A highly testable and diagnosable fabrication process test chip. ITC 1998: 853-861
8		Dilip K. Bhavsar, Yervant Zorian: ITC 97 Panel Sessions. IEEE Design & Test of Computers 15(1): 7, 91 (1998)
1997
7	EE	Dilip K. Bhavsar, John H. Edmondson: Alpha 21164 Testability Strategy. IEEE Design & Test of Computers 14(1): 25-33 (1997)
1994
6		Dilip K. Bhavsar, John H. Edmondson: Testability Strategy of the ALPHA AXP 21164 Microprocessor. ITC 1994: 50-59
1991
5		Dilip K. Bhavsar: An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes. ITC 1991: 768-776
4	EE	Dilip K. Bhavsar: Testing Interconnections to Static RAMs. IEEE Design & Test of Computers 8(2): 63-71 (1991)
1985
3		Dilip K. Bhavsar: "Concatenable Polydividers": Bit-Sliced LFSR Chips for Board Self-Test. ITC 1985: 88-93
1984
2		Dilip K. Bhavsar, Balakrishnan Krishnamurthy: Can We Eliminate Fault Escape in Self-Testing by Polynomial Division (Signature Analysis) ? ITC 1984: 134-139
1981
1		Dilip K. Bhavsar, Richard W. Heckelman: Self-Testing by Polynomial Division. ITC 1981: 208-216

Coauthor Index

1	David R. Akeson	[9] [10]
2	Vijay Bettada	[18]
3	William J. Bowhill	[9]
4	Richard A. Davies	[16] [17] [18]
5	Ugonna Echeruo	[9]
6	John H. Edmondson	[6] [7]
7	Scott Erlanger	[17]
8	Michael K. Gowan	[10]
9	Joel Grodstein	[18]
10	Richard W. Heckelman	[1]
11	Daniel B. Jackson	[10]
12	Balakrishnan Krishnamurthy	[2]
13	Rishan Tan	[15]
14	Yervant Zorian	[8]

Colors in the list of coauthors