| 2004 |
| 16 | EE | John M. Hitchcock,
Aduri Pavan,
Pramodchandran N. Variyam:
Partial Bi-Immunity and NP-Completeness
Electronic Colloquium on Computational Complexity (ECCC)(025): (2004) |
| 2003 |
| 15 | EE | Kranthi K. Pinjala,
Bruce C. Kim,
Pramodchandran N. Variyam:
Automatic Diagnostic Program Generation for Mixed Signal Load Board.
ITC 2003: 403-409 |
| 2002 |
| 14 | EE | Achintya Halder,
Abhijit Chatterjee,
Pramodchandran N. Variyam,
John Ridley:
Measuring Stray Capacitance on Tester Hardware.
VTS 2002: 351-356 |
| 13 | EE | Pramodchandran N. Variyam,
Sasikumar Cherubal,
Abhijit Chatterjee:
Prediction of analog performance parameters using fast transienttesting.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 349-361 (2002) |
| 2000 |
| 12 | | Pramodchandran N. Variyam:
Increasing the IDDQ test resolution using current prediction.
ITC 2000: 217-224 |
| 11 | | Pramodchandran N. Variyam,
Vinay Agrawal:
Measuring code edges of ADCs using interpolation and its application to offset and gain error testing.
ITC 2000: 349-357 |
| 10 | EE | Pramodchandran N. Variyam,
Abhijit Chatterjee:
Digital-Compatible BIST for Analog Circuits Using Transient Response Sampling.
IEEE Design & Test of Computers 17(3): 106-115 (2000) |
| 9 | EE | Pramodchandran N. Variyam,
Abhijit Chatterjee:
Specification-driven test generation for analog circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1189-1201 (2000) |
| 1999 |
| 8 | EE | Pramodchandran N. Variyam,
Junwei Hou,
Abhijit Chatterjee:
Test Generation for Analog Circuits Using Partial Numerical Simulation.
VLSI Design 1999: 597-602 |
| 7 | EE | Pramodchandran N. Variyam,
Junwei Hou,
Abhijit Chatterjee:
Efficient Test Generation for Transient Testing of Analog Circuits Using Partial Numerical Simulation.
VTS 1999: 214-219 |
| 1998 |
| 6 | EE | Pramodchandran N. Variyam,
Abhijit Chatterjee:
Specification-Driven Test Design for Analog Circuits.
DFT 1998: 335-340 |
| 5 | EE | Pramodchandran N. Variyam,
Abhijit Chatterjee:
Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements.
VTS 1998: 132-137 |
| 4 | EE | Heebyung Yoon,
Pramodchandran N. Variyam,
Abhijit Chatterjee,
Naveena Nagi:
Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits.
VTS 1998: 145-151 |
| 1997 |
| 3 | EE | Pramodchandran N. Variyam,
Abhijit Chatterjee:
Test generation for comprehensive testing of linear analog circuits using transient response sampling.
ICCAD 1997: 382-385 |
| 2 | EE | Pramodchandran N. Variyam,
Abhijit Chatterjee:
FLYER: Fast Fault Simulation of Linear Analog Circuits Using Polynomial Waveform and Perturbed State Representation.
VLSI Design 1997: 408-412 |
| 1 | EE | Pramodchandran N. Variyam,
Abhijit Chatterjee,
Naveena Nagi:
Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling.
VTS 1997: 261-266 |