Jayashree Saxena

2004
14	EE	Kenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington: Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques. ITC 2004: 355-364
2003
13	EE	Jayashree Saxena, Kenneth M. Butler, Vinay B. Jayaram, Subhendu Kundu, N. V. Arvind, Pravin Sreeprakash, Manfred Hachinger: A Case Study of IR-Drop in Structured At-Speed Testing. ITC 2003: 1098-1104
2002
12	EE	Jayashree Saxena, Kenneth M. Butler, John Gatt, R. Raghuraman, Sudheendra Phani Kumar, Supatra Basu, David J. Campbell, John Berech: Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges . ITC 2002: 1120-1129
2001
11		Jayashree Saxena, Kenneth M. Butler, Lee Whetsel: An analysis of power reduction techniques in scan testing. ITC 2001: 670-677
2000
10		Jayashree Saxena, Kenneth M. Butler: An empirical study on the effects of test type ordering on overall test efficiency. ITC 2000: 408-416
9		Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler: Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. ITC 2000: 729-738
1998
8	EE	Jayashree Saxena: IC diagnosis: preventing wars and war stories. ITC 1998: 1138
7	EE	Jayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess: On applying non-classical defect models to automated diagnosis. ITC 1998: 748-757
1997
6		David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess, Jayashree Saxena, Kenneth M. Butler: Bridging Fault Diagnosis in the Absence of Physical Information. ITC 1997: 887-893
5	EE	Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Kinra, Jayashree Saxena: Automated Diagnosis in Testing and Failure Analysis. IEEE Design & Test of Computers 14(3): 83-89 (1997)
1996
4		Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Jones, Jayashree Saxena: Integrating Automated Diagnosis into the Testing and Failure Analysis Operations. ITC 1996: 934
1995
3	EE	Dhiraj K. Pradhan, Jayashree Saxena: A novel scheme to reduce test application time in circuits with full scan. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1577-1586 (1995)
1993
2		Jayashree Saxena, Dhiraj K. Pradhan: Desgin for Testability of Asynchronous Sequential Circuits. ICCD 1993: 518-522
1		Jayashree Saxena, Dhiraj K. Pradhan: A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits. ITC 1993: 724-733

Coauthor Index

1	N. V. Arvind	[13]
2	Hari Balachandran	[7] [9]
3	Supatra Basu	[12]
4	John Berech	[12]
5	Kenneth M. Butler	[4] [5] [6] [7] [9] [10] [11] [12] [13] [14]
6	David J. Campbell	[12]
7	Brian Chess	[6] [7]
8	F. Joel Ferguson	[6] [7]
9	Tony Fryars	[14]
10	John Gatt	[12]
11	Manfred Hachinger	[13]
12	Graham Hetherington	[14]
13	Vinay B. Jayaram	[13]
14	Karl Johnson	[4] [5]
15	Anjali Jones	[4]
16	Anjali Kinra	[5]
17	Sudheendra Phani Kumar	[12]
18	Subhendu Kundu	[13]
19	Fred Lakbani	[9]
20	Tracy Larrabee	[6] [7]
21	David B. Lavo	[6] [7]
22	Jeff Platt	[4] [5]
23	Dhiraj K. Pradhan	[1] [2] [3]
24	R. Raghuraman	[12]
25	Pravin Sreeprakash	[13]
26	Zoran Stanojevic	[9]
27	D. M. H. Walker (Duncan M. Hank Walker)	[9]
28	Lee Whetsel	[11]

Colors in the list of coauthors