2009 | ||
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113 | EE | Franco Fummi, Mirko Loghi, Massimo Poncino, Graziano Pravadelli: A cosimulation methodology for HW/SW validation and performance estimation. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009) |
2008 | ||
112 | EE | Andrea Acquaviva, Franco Fummi, Giovanni Perbellini, Davide Quaglia: An energy-aware co-simulation framework for the design of wireless sensor networks. ACM Great Lakes Symposium on VLSI 2008: 375-378 |
111 | EE | Nicola Bombieri, Nicola Deganello, Franco Fummi: Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation. DATE 2008: 15-20 |
110 | EE | Nicola Bombieri, Franco Fummi, Graziano Pravadelli: A Mutation Model for the SystemC TLM 2.0 Communication Interfaces. DATE 2008: 396-401 |
109 | EE | Franco Fummi, Davide Quaglia, Francesco Stefanni: Network Fault Model for Dependability Assessment of Networked Embedded Systems. DFT 2008: 54-62 |
108 | EE | Franco Fummi, Davide Quaglia, Francesco Stefanni: A SystemC-based Framework for Modeling and Simulation of Networked Embedded Systems. FDL 2008: 49-54 |
107 | EE | Luidi Di Guglielmo, Franco Fummi, Graziano Pravadelli: Vacuity Analysis by Fault Simulation. MEMOCODE 2008: 27-36 |
106 | EE | Nicola Bombieri, Franco Fummi, Graziano Pravadelli: Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) |
2007 | ||
105 | EE | E. Alessio, Franco Fummi, Davide Quaglia, Maura Turolla: Modeling and simulation alternatives for the design of networked embedded systems. DATE 2007: 1030-1035 |
104 | EE | Franco Fummi, Giovanni Perbellini, R. Pietrangeli, Davide Quaglia: Interactive presentation: A middleware-centric design flow for networked embedded systems. DATE 2007: 1048-1053 |
103 | EE | Paolo Destro, Franco Fummi, Graziano Pravadelli: A smooth refinement flow for co-designing HW and SW threads. DATE 2007: 105-110 |
102 | EE | Paolo Azzoni, Massimo Bertoletti, Nicola Dragone, Franco Fummi, Carlo Guardiani, W. Vendraminetto: Yield-aware placement optimization. DATE 2007: 1232-1237 |
101 | EE | Nicola Bombieri, Franco Fummi, Graziano Pravadelli: Incremental ABV for functional validation of TL-to-RTL design refinement. DATE 2007: 882-887 |
100 | EE | Nicola Bombieri, Franco Fummi, Graziano Pravadelli, João Marques-Silva: Towards Equivalence Checking Between TLM and RTL Models. MEMOCODE 2007: 113-122 |
99 | EE | Franco Fummi, Cristina Marconcini, Graziano Pravadelli, Ian G. Harris: A CLP-Based Functional ATPG for Extended FSMs. MTV 2007: 98-105 |
98 | EE | Michele Borgatti, Andrea Capello, Umberto Rossi, Jean-Luc Lambert, Imed Moussa, Franco Fummi, Graziano Pravadelli: An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems CoRR abs/0710.4846: (2007) |
97 | EE | Nicola Bombieri, Franco Fummi, Graziano Pravadelli, Andrea Fedeli: Hybrid, Incremental Assertion-Based Verification for TLM Design Flows. IEEE Design & Test of Computers 24(2): 140-152 (2007) |
96 | EE | Andrea Fedeli, Franco Fummi, Graziano Pravadelli: Properties Incompleteness Evaluation by Functional Verification. IEEE Trans. Computers 56(4): 528-544 (2007) |
95 | EE | Franco Fummi, Graziano Pravadelli: Too Few or Too Many Properties? Measure it by ATPG! J. Electronic Testing 23(5): 373-388 (2007) |
94 | EE | Franco Fummi, Giovanni Perbellini: eEPC: an EPCglobal-compliant Embedded Architecture for RFID-based Solutions. JCM 2(7): 49-58 (2007) |
2006 | ||
93 | EE | Franco Fummi, Giovanni Perbellini, Mirko Loghi, Massimo Poncino: ISS-centric modular HW/SW co-simulation. ACM Great Lakes Symposium on VLSI 2006: 31-36 |
92 | EE | Nicola Bombieri, Franco Fummi, Davide Quaglia: TLM/network design space exploration for networked embedded systems. CODES+ISSS 2006: 58-63 |
91 | EE | Nicola Bombieri, Franco Fummi, Graziano Pravadelli: On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL. DATE 2006: 1007-1012 |
90 | EE | Franco Fummi, Davide Quaglia, Fabio Ricciato, Maura Turolla: Modeling and simulation of mobile gateways interacting with wireless sensor networks. DATE Designers' Forum 2006: 106-111 |
89 | EE | Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli: FATE: a Functional ATPG to Traverse Unstabilized EFSMs. European Test Symposium 2006: 179-184 |
88 | EE | Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli: EFSM Manipulation to Increase High-Level ATPG Effectiveness. ISQED 2006: 57-62 |
87 | EE | Nicola Bombieri, Franco Fummi, Graziano Pravadelli: A methodology for abstracting RTL designs into TL descriptions. MEMOCODE 2006: 103-112 |
86 | EE | Nicola Bombieri, Franco Fummi, Graziano Pravadelli: Hardware Design and Simulation for Verification. SFM 2006: 1-29 |
85 | EE | Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli: Improving Gate-Level ATPG by Traversing Concurrent EFSMs. VTS 2006: 172-179 |
84 | EE | Ian G. Harris, Franco Fummi: Guest Editor's Introduction. International Journal of Parallel Programming 34(1): 1-2 (2006) |
2005 | ||
83 | EE | Franco Fummi, Cristina Marconcini, Graziano Pravadelli: An EFSM-based approach for functional ATPG. ACM Great Lakes Symposium on VLSI 2005: 197-200 |
82 | EE | Franco Fummi, Mirko Loghi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino: Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation. DATE 2005: 798-803 |
81 | EE | Nicola Bombieri, Franco Fummi, Graziano Pravadelli: Functional Verification of Networked Embedded Systems. ISQED 2005: 321-326 |
80 | EE | Stefano Brait, Franco Fummi, Graziano Pravadelli: On the use of a high-level fault model to analyze logical consequence of properties. MEMOCODE 2005: 221-230 |
79 | EE | Nicola Bombieri, Andrea Fedeli, Franco Fummi: Extended abstract: on the property-based verification in SoC design flow founded on transaction level modeling. MEMOCODE 2005: 239-240 |
78 | EE | Nicola Bombieri, Andrea Fedeli, Franco Fummi: On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling. MTV 2005: 127-132 |
77 | EE | Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli: A Pseudo-Deterministic Functional ATPG based on EFSM Traversing. MTV 2005: 70-75 |
76 | EE | Franco Fummi, Stefano Martini, Giovanni Perbellini, Fabio Ricciato, Maura Turolla: Embedded SW Design Issues for Distributed Applications on Mobile Terminals. MobiQuitous 2005: 507-509 |
75 | EE | Franco Fummi, Cristina Marconcini, Graziano Pravadelli: Logic-level mapping of high-level faults. Integration 38(3): 467-490 (2005) |
74 | EE | Franco Fummi, Ian G. Harris: Editorial. International Journal of Parallel Programming 33(6): 583-584 (2005) |
2004 | ||
73 | EE | Franco Fummi, Graziano Pravadelli: Logic-level analysis of high-level faults. ACM Great Lakes Symposium on VLSI 2004: 100-103 |
72 | EE | Luca Formaggio, Franco Fummi, Graziano Pravadelli: A timing-accurate HW/SW co-simulation of an ISS with SystemC. CODES+ISSS 2004: 152-157 |
71 | EE | Franco Fummi, Stefano Martini, Giovanni Perbellini, Massimo Poncino, Fabio Ricciato, Maura Turolla: Heterogeneous Co-Simulation of Networked Embedded Systems. DATE 2004: 168-173 |
70 | EE | Michele Borgatti, Andrea Capello, Umberto Rossi, Jean-Luc Lambert, Imed Moussa, Franco Fummi, Graziano Pravadelli: An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems. DATE 2004: 266-271 |
69 | EE | Michele Borgatti, Andrea Capello, Umberto Rossi, Jean-Luc Lambert, Imed Moussa, Franco Fummi, Graziano Pravadelli: An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems. DATE 2004: 266-271 |
68 | Franco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino: Modeling and Analysis of Heterogeneous Industrial Networks Architectures. DATE 2004: 342-344 | |
67 | EE | Franco Fummi, Stefano Martini, Giovanni Perbellini, Massimo Poncino: Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC. DATE 2004: 564-569 |
66 | EE | Nicola Bombieri, Franco Fummi, Graziano Pravadelli: At-Speed Functional Verification of Programmable Devices. DFT 2004: 386-394 |
65 | EE | Franco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino: Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures. ICCD 2004: 496-501 |
64 | EE | Michele Borgatti, Andrea Fedeli, Umberto Rossi, Jean-Luc Lambert, Imed Moussa, Franco Fummi, Cristina Marconcini, Graziano Pravadelli: A Verification Methodology for Reconfigurable Systems. MTV 2004: 85-90 |
2003 | ||
63 | EE | Alessandro Fin, Franco Fummi, Graziano Pravadelli: Mixing ATPG and property checking for testing HW/SW interfaces. ACM Great Lakes Symposium on VLSI 2003: 303-306 |
62 | EE | Franco Fummi, Giovanni Perbellini, Paolo Gallo, Massimo Poncino, Stefano Martini, Fabio Ricciato: A timing-accurate modeling and simulation environment for networked embedded systems. DAC 2003: 42-47 |
61 | EE | Nicola Drago, Franco Fummi, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino: Estimation of Bus Performance for a Tuplespace in an Embedded Architecture. DATE 2003: 20188-20195 |
60 | EE | Alessandro Fin, Franco Fummi: LAERTE++: an Object Oriented High-level TPG for SystemC Designs. FDL 2003: 658-668 |
59 | EE | Franco Fummi: The Confluence of Manufacturing Test and Design Validation. ITC 2003: 1291 |
58 | EE | Franco Fummi, Graziano Pravadelli, Andrea Fedeli, Umberto Rossi, Franco Toto: On the Use of a High-Level Fault Model to Check Properties Incompleteness. MEMOCODE 2003: 145-152 |
57 | EE | Alessandro Fin, Franco Fummi, Massimo Poncino, Graziano Pravadelli: A SystemC-based Framework for Properties Incompleteness Evaluation. MTV 2003: 89-94 |
56 | EE | Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino: SystemC Cosimulation and Emulation of Multiprocessor SoC Designs. IEEE Computer 36(4): 53-59 (2003) |
55 | EE | Fabrizio Ferrandi, Franco Fummi, Graziano Pravadelli, Donatella Sciuto: Identification of design errors through functional testing. IEEE Transactions on Reliability 52(4): 400-412 (2003) |
2002 | ||
54 | EE | Paolo Azzoni, Andrea Fedeli, Franco Fummi, Graziano Pravadelli, Umberto Rossi, Franco Toto: An error simulation based approach to measure error coverage of formal properties. ACM Great Lakes Symposium on VLSI 2002: 53-58 |
53 | EE | Alessandro Fin, Franco Fummi: Protected IP-core test generation. ACM Great Lakes Symposium on VLSI 2002: 59-64 |
52 | EE | A. Castelnuovo, Alessandro Fin, Franco Fummi, F. Sforza: Emulation-Based Design Errors Identification. DFT 2002: 365-371 |
51 | Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick: Functional Test Generation For Digital Integrated Circuits Using A Genetic Algorithm. GECCO 2002: 1275 | |
50 | EE | Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino: Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip. ICCD 2002: 494-499 |
49 | EE | Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick: A Genetic Testing Framework for Digital Integrated Circuits. ICTAI 2002: 521-526 |
48 | EE | S. Cailotto, Alessandro Fin, Franco Fummi: A fault tolerant incremental design methodology. ISCAS (3) 2002: 161-164 |
47 | EE | Maurizio Martignano, Nicola Drago, Franco Fummi, Stefano Martini: A combined approach to validate the design of embedded network devices. ISCAS (3) 2002: 169-172 |
46 | EE | Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto: Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications. IEEE Trans. Computers 51(2): 200-215 (2002) |
2001 | ||
45 | EE | Alessandro Fin, Franco Fummi, Maurizio Martignano, Mirko Signoretto: SystemC: a homogenous environment to test embedded systems. CODES 2001: 17-22 |
44 | EE | Fabrizio Ferrandi, G. Ferrara, Donatella Sciuto, Alessandro Fin, Franco Fummi: Functional test generation for behaviorally sequential models. DATE 2001: 403-410 |
43 | Alessandro Fin, Franco Fummi, Giovanni Perbellini: Soft-cores generation by instruction set analysis. ISSS 2001: 227-232 | |
42 | Alessandro Fin, Franco Fummi, Graziano Pravadelli: AMLETO: a multi-language environment for functional test generation. ITC 2001: 821-829 | |
41 | EE | Franco Fummi, Marco Boschini, Xiaoming Yu, Elizabeth M. Rudnick: Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach. J. Electronic Testing 17(3-4): 321-330 (2001) |
2000 | ||
40 | EE | Alessandro Fin, Franco Fummi: A Web-CAD methodology for IP-core analysis and simulation. DAC 2000: 597-600 |
39 | EE | Alessandro Fin, Franco Fummi: A VHDL Error Simulator for Functional Test Generation. DATE 2000: 390-395 |
38 | EE | G. Biasoli, Fabrizio Ferrandi, Donatella Sciuto, Alessandro Fin, Franco Fummi: BIST Architectures Selection Based on Behavioral Testing. DFT 2000: 292-298 |
37 | EE | Fabrizio Ferrandi, Donatella Sciuto, Alessandro Fin, Franco Fummi: An Application of Genetic Algorithms and BDDs to Functional Testing. ICCD 2000: 48- |
36 | EE | Fabrizio Ferrandi, G. Fornara, Donatella Sciuto, G. Ferrara, Franco Fummi: Testability Alternatives Exploration through Functional Testing. VTS 2000: 423-430 |
35 | EE | Franco Fummi, Donatella Sciuto: A Hierarchical Test Generation Approach for Large Controllers. IEEE Trans. Computers 49(4): 289-302 (2000) |
34 | EE | Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto: Symbolic optimization of interacting controllers based onredundancy identification and removal. IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 760-772 (2000) |
1999 | ||
33 | EE | Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto: Symbolic Functional Vector Generation for VHDL Specifications. DATE 1999: 442- |
32 | EE | Marco Brazzarola, Franco Fummi: Power Characterization of LFSRs. DFT 1999: 139-147 |
31 | EE | Marco Brera, Fabrizio Ferrandi, Donatella Sciuto, Franco Fummi: Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information. DFT 1999: 174-180 |
30 | EE | Franco Fummi, Donatella Sciuto, Micaela Serra: Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal. IEEE Trans. Computers 48(12): 1305-1323 (1999) |
1998 | ||
29 | EE | Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino: Power Estimation of Behavioral Descriptions. DATE 1998: 762-766 |
28 | EE | Franco Fummi, A. Marshall, Laura Pozzi, Mariagiovanna Sami: Minimizing the Application Time for Manufacturer Testing of FPGA (Abstract). FPGA 1998: 258 |
27 | EE | F. S. Bietti, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto: VHDL Testability Analysis Based on Fault Clustering and Implicit Fault Injection. Great Lakes Symposium on VLSI 1998: 237-242 |
26 | EE | Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto: Implicit test generation for behavioral VHDL models. ITC 1998: 587- |
25 | EE | Franco Fummi, Donatella Sciuto, Cristina Silvano: Automatic generation of error control codes for computer applications. IEEE Trans. VLSI Syst. 6(3): 502-506 (1998) |
24 | EE | Cesare Alippi, Franco Fummi, Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto: Testability analysis and behavioral testing of the Hopfield neural paradigm. IEEE Trans. VLSI Syst. 6(3): 507-511 (1998) |
1997 | ||
23 | EE | Fabrizio Ferrandi, Franco Fummi, Laura Pozzi, Mariagiovanna Sami: Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays. DFT 1997: 85-93 |
22 | EE | Franco Fummi, Mariagiovanna Sami, F. Tartarini: Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems. Great Lakes Symposium on VLSI 1997: 118-123 |
21 | EE | Giacomo Buonanno, Fabrizio Ferrandi, L. Ferrandi, Franco Fummi, Donatella Sciuto: How an "Evolving" Fault Model Improves the Behavioral Test Generation. Great Lakes Symposium on VLSI 1997: 124- |
20 | M. Bacis, Giacomo Buonanno, Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto: Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels. ICCD 1997: 654-658 | |
19 | EE | Franco Fummi, Donatella Sciuto: Implicit test pattern generation constrained to cellular automata embedding. VTS 1997: 54-59 |
18 | EE | Franco Fummi, U. Rovati, Donatella Sciuto: Functional design for testability of control-dominated architectures. ACM Trans. Design Autom. Electr. Syst. 2(2): 98-122 (1997) |
17 | EE | Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto, Enrico Macii, Massimo Poncino: Testing Core-Based Systems: A Symbolic Methodology. IEEE Design & Test of Computers 14(4): 69-77 (1997) |
16 | EE | Franco Fummi, Donatella Sciuto: A complete testing strategy based on interacting and hierarchical FSMs. Integration 23(1): 75-93 (1997) |
1996 | ||
15 | EE | Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto: Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques. DAC 1996: 467-470 |
14 | EE | Roberto Bevacqua, Luca Guerrazzi, Franco Fummi: SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation. EUROMICRO 1996: 351- |
13 | EE | Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto: Test Generation for Networks of Interacting FSMs Using Symbolic Techniques. Great Lakes Symposium on VLSI 1996: 208-213 |
12 | EE | Roberto Bevacqua, Luca Guerrazzi, Fabrizio Ferrandi, Franco Fummi: Implicit Test Sequences Compaction for Decreasing Test Application Cos. ICCD 1996: 384-382 |
1995 | ||
11 | EE | Franco Fummi, U. Rovati, Donatella Sciuto: Testable synthesis of high complex control devices. EURO-DAC 1995: 117-122 |
10 | EE | Franco Fummi, Donatella Sciuto, M. Serro: Synthesis for testability of large complexity controllers. ICCD 1995: 180- |
9 | Cristiana Bolchini, Franco Fummi, R. Gemelli, Fabio Salice: A BDD Based Algorithm for Detecting Difficult Faults. ISCAS 1995: 2015-2018 | |
8 | EE | Giacomo Buonanno, Franco Fummi, Donatella Sciuto: TIES: A testability increase expert system for VLSI design. J. Electronic Testing 6(2): 203-217 (1995) |
1994 | ||
7 | Franco Fummi, Donatella Sciuto, Micaela Serra: Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: A Mixed Functional/Structural Method. DFT 1994: 254-262 | |
6 | Franco Fummi, Donatella Sciuto, Micaela Serra: A Functional Approach to Delay Faults Test Generation for Sequential Circuits. EDAC-ETC-EUROASIC 1994: 51-57 | |
5 | Alessandro Balboni, Claudio Costi, Franco Fummi, Donatella Sciuto: From Behavioral Description to Systolic Array Based Architectures. EDAC-ETC-EUROASIC 1994: 657 | |
4 | Cristiana Bolchini, Franco Fummi, Donatella Sciuto: Two-Dimensional Sequential Array Architectures: Design for Testability Approaches. ISCAS 1994: 81-84 | |
1993 | ||
3 | Giacomo Buonanno, Franco Fummi, Donatella Sciuto: Fault Detection in Sequential Circuits through Functional Testing. DFT 1993: 191-198 | |
2 | Giacomo Buonanno, Franco Fummi, Donatella Sciuto: Functional Fault Models and Gate Level Coverage for Sequential Architectures. ICCD 1993: 572-575 | |
1 | Giacomo Buonanno, Franco Fummi, Donatella Sciuto: Functional Testing and Constrained Synthesis of Sequential Architectures. ISCAS 1993: 1523-1526 |